📄 main.lst
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217 2 return the ACK and the data in the same packet, so we need to handle
218 2 that case. */
219 2 // if (data_ptr != PTR_NULL)
220 2 // {
221 2 // status = mn_send(socket_no,data_ptr,data_len);
222 2 //
223 2 // if (status > 0 && socket_ptr->recv_len > 0)
224 2 // {
225 2 // data_ptr = socket_ptr->recv_ptr;
226 2 // data_len = socket_ptr->recv_len;
227 2 // continue;
228 2 // }
229 2 // }
230 2
231 2 // if (status < 0 || socket_ptr->tcp_state == TCP_CLOSED)
232 2 // {
233 2 // break;
234 2
235 2 // }
236 2 do
237 2 {
238 3
239 3 err = mn_recv(socket_no,data_buf,10);
240 3
C51 COMPILER V8.02 MAIN 08/27/2007 11:39:16 PAGE 5
241 3 }while (err == NEED_TO_LISTEN);
242 2
243 2 if (err < 0)
244 2 {
245 3
246 3 if(err==SOCKET_TIMED_OUT)continue;
247 3 mn_abort(socket_no);
248 3 return;
249 3 }
250 2
251 2 // if we got something, send back what we got
252 2 if (err > 0)
253 2 {
254 3
255 3 data_len = err;
256 3
257 3 for(i=0;i<data_len;i++)
258 3 {
259 4 if(data_buf[i]!=statusnum)status=1;
260 4
261 4 statusnum++;
262 4
263 4 if(statusnum==10)statusnum=0;
264 4
265 4 }
266 3
267 3 continue;
268 3
269 3 }
270 2
271 2 }
272 1
273 1 return;
274 1
275 1
276 1 }
277
278
279 //-----------------------------------------------------------------------------
280 // Initialization Routines
281 //-----------------------------------------------------------------------------
282
283 //-----------------------------------------------------------------------------
284 // PORT_Init
285 //-----------------------------------------------------------------------------
286 //
287 // Configure the Interrupts, Crossbar and GPIO ports
288 //
289 void PORT_Init (void)
290 {
291 1 char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
292 1
293 1 SFRPAGE = CONFIG_PAGE; // set SFR page
294 1 P1MDOUT |= 0x40; // Set P1.6(TB_LED) to push-pull
295 1 P2MDOUT |= 0x08; // Set P2.2(AB4_LED1)
296 1 // all pins used by the external memory interface are in push-pull mode
297 1 P4MDOUT = 0xDF;
298 1 P5MDOUT = 0xFF;
299 1 P6MDOUT = 0xFF;
300 1 P7MDOUT = 0xFF;
301 1 P4 = 0xC0; // /WR, /RD, are high, RESET is low
302 1 P5 = 0xFF;
C51 COMPILER V8.02 MAIN 08/27/2007 11:39:16 PAGE 6
303 1 P6 = 0xFF; // P5, P6 contain the address lines
304 1 P7 = 0xFF; // P7 contains the data lines
305 1
306 1 TCON &= ~0x01; // Make /INT0 level triggered
307 1
308 1 // Enable UART0, CP0, and /INT0. This puts /INT0 on P0.3.
309 1 XBR0 = 0x84;
310 1 XBR1 = 0x04;
311 1 XBR2 = 0x40;
312 1 SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
313 1
314 1 }
315
316 //-----------------------------------------------------------------------------
317 // EMIF_Init
318 //-----------------------------------------------------------------------------
319 //
320 // Configure the External Memory Interface for both on and off-chip access.
321 //
322 void EMIF_Init (void)
323 {
324 1 char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
325 1
326 1 SFRPAGE = LEGACY_PAGE;
327 1
328 1 EMI0CF = 0xFB; // Split-mode, non-multiplexed on P0 - P3
329 1
330 1 EMI0TC = EMIF_TIMING; // This constant may be modified
331 1 // according to SYSCLK to meet the
332 1 // timing requirements for the CP2200
333 1
334 1 EMI0CN = BASE_ADDRESS; // Page of XRAM accessed by EMIF
335 1 SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
336 1
337 1 }
338
339 //-----------------------------------------------------------------------------
340 // SYSCLK_Init
341 //-----------------------------------------------------------------------------
342 //
343 // This routine initializes the system clock.
344 //
345 void SYSCLK_Init (void)
346 {
347 1 int i; // software timer
348 1
349 1 char SFRPAGE_SAVE = SFRPAGE; // Save Current SFR page
350 1
351 1 SFRPAGE = CONFIG_PAGE; // set SFR page
352 1
353 1 OSCICN = 0x83; // set internal oscillator to run
354 1 // at its maximum frequency
355 1
356 1 CLKSEL = 0x00; // Select the internal osc. as
357 1 // the SYSCLK source
358 1 //Turn on the PLL and increase the system clock by a factor of M/N
359 1 PLL0CN = 0x00; // Set internal osc. as PLL source
360 1 SFRPAGE = LEGACY_PAGE;
361 1 FLSCL = 0x30; // Set FLASH read time for 100 MHz clk
362 1 SFRPAGE = CONFIG_PAGE;
363 1
364 1 PLL0CN |= 0x01; // Enable Power to PLL
C51 COMPILER V8.02 MAIN 08/27/2007 11:39:16 PAGE 7
365 1
366 1 PLL0DIV = 0x01; // Set Pre-divide value to N (N = 1)
367 1 PLL0MUL = 0x04; // Multiply SYSCLK by M (M=4)
368 1 PLL0FLT = 0x01; // Set the PLL filter register for
369 1 // a reference clock from 12.2 - 19.5 MHz
370 1 // and an output clock from 65 - 100 MHz
371 1 for (i=0; i < 256; i++) ; // Wait at least 5us
372 1 PLL0CN |= 0x02; // Enable the PLL
373 1 while(!(PLL0CN & 0x10)); // Wait until PLL frequency is locked
374 1 CLKSEL = 0x02; // Select PLL as SYSCLK source
375 1
376 1 SFRPAGE = SFRPAGE_SAVE; // Restore SFR page
377 1
378 1 }
379
380 //-----------------------------------------------------------------------------
381 // ether_reset_low
382 //-----------------------------------------------------------------------------
383 //
384 // This routine drives the reset pin of the ethernet controller low.
385 //
386 void ether_reset_low()
387 {
388 1
389 1 unsigned char SFRPAGE_Save;
390 1
391 1 SFRPAGE_Save = SFRPAGE; // Save Current SFR page
392 1 SFRPAGE = CONFIG_PAGE; // Switch to ports SFR page
393 1
394 1 P4 &= ~0x20; // Pull reset low
395 1
396 1 SFRPAGE = SFRPAGE_Save; // Restore SFR page
397 1
398 1 }
399
400 //-----------------------------------------------------------------------------
401 // ether_reset_high
402 //-----------------------------------------------------------------------------
403 //
404 // This routine places the reset pin in High-Z allowing it to be pulled up
405 // using the external pull-up resistor.
406 //
407 // Additionally, this routine waits for the reset pin to read high before
408 // exiting.
409 //
410 void ether_reset_high (void)
411 {
412 1
413 1 unsigned char SFRPAGE_Save;
414 1
415 1 SFRPAGE_Save = SFRPAGE; // Save Current SFR page
416 1 SFRPAGE = CONFIG_PAGE; // Switch to ports SFR page
417 1
418 1 P4 |= 0x20; // Allow /RST to rise
419 1 while(!(P4 & 0x20)); // Wait for /RST to go high
420 1
421 1 SFRPAGE = SFRPAGE_Save; // Restore SFR page
422 1
423 1
424 1 }
C51 COMPILER V8.02 MAIN 08/27/2007 11:39:16 PAGE 8
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 554 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 104 1310
PDATA SIZE = ---- ----
DATA SIZE = ---- ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 1 WARNING(S), 0 ERROR(S)
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