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📄 firt.mdl

📁 是一个基于MATLAB /simulink/DSP BUILDER 的fir数字滤波器的设计
💻 MDL
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    Block {
      BlockType		      Reference
      Name		      "Product"
      Ports		      [2, 1]
      Position		      [415, 157, 485, 228]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product AlteraBlockSet"
      pipeline		      "0"
      lpm		      off
      eab		      off
      clken		      off
      MaskValue		      "1"
      SIGNALCOMPILER_PARAMS   "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"0;"
    }
    Block {
      BlockType		      Reference
      Name		      "Product1"
      Ports		      [2, 1]
      Position		      [420, 282, 490, 353]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product AlteraBlockSet"
      pipeline		      "0"
      lpm		      off
      eab		      off
      clken		      off
      MaskValue		      "1"
      SIGNALCOMPILER_PARAMS   "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"0;"
    }
    Block {
      BlockType		      Reference
      Name		      "Product2"
      Ports		      [2, 1]
      Position		      [425, 402, 495, 473]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product AlteraBlockSet"
      pipeline		      "0"
      lpm		      off
      eab		      off
      clken		      off
      MaskValue		      "1"
      SIGNALCOMPILER_PARAMS   "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"0;"
    }
    Block {
      BlockType		      Reference
      Name		      "Product3"
      Ports		      [2, 1]
      Position		      [440, 537, 510, 608]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product AlteraBlockSet"
      pipeline		      "0"
      lpm		      off
      eab		      off
      clken		      off
      MaskValue		      "1"
      SIGNALCOMPILER_PARAMS   "clken;off;eab;off;lpm;off;MaskValue;1;pipeline;"
"0;"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [2]
      Position		      [760, 305, 795, 360]
      Floating		      off
      Location		      [233, 359, 557, 598]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      YMin		      "-5~-5"
      YMax		      "5~5"
      DataFormat	      "StructureWithTime"
      SampleTime	      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [769, 143, 838, 190]
      ForegroundColor	      "blue"
      SourceBlock	      "Altelink/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "APEX 20K"
      opt		      "Balanced"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "D:\\altera\\quartus60\\work1\\fir"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    off
      JTAGCable		      "USB-Blaster [USB-0]"
      dspb_ver		      "5.1"
    }
    Block {
      BlockType		      Reference
      Name		      "h1"
      Description	      "Sign Binary Fractionnal"
      Ports		      [0, 1]
      Position		      [135, 222, 200, 238]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/AltBus"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Constant"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "63"
      LocPin		      "any"
      cst		      "63"
      modulename	      "h1"
      ppat		      "D:\\altera\\quartus60\\work1\\fir\\DSPBuilder_f"
"irt"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Constant;bwl;8;bwr;"
"0;sat;off;rnd;off;cst;63;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "h2"
      Description	      "Sign Binary Fractionnal"
      Ports		      [0, 1]
      Position		      [145, 347, 210, 363]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/AltBus"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Constant"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "127"
      LocPin		      "any"
      cst		      "127"
      modulename	      "h2"
      ppat		      "D:\\altera\\quartus60\\work1\\fir\\DSPBuilder_f"
"irt"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Constant;bwl;8;bwr;"
"0;sat;off;rnd;off;cst;127;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "h3"
      Description	      "Sign Binary Fractionnal"
      Ports		      [0, 1]
      Position		      [145, 477, 210, 493]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/AltBus"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Constant"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "127"
      LocPin		      "any"
      cst		      "127"
      modulename	      "h3"
      ppat		      "D:\\altera\\quartus60\\work1\\fir\\DSPBuilder_f"
"irt"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Constant;bwl;8;bwr;"
"0;sat;off;rnd;off;cst;127;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "h4"
      Description	      "Sign Binary Fractionnal"
      Ports		      [0, 1]
      Position		      [160, 592, 225, 608]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/AltBus"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Constant"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "63"
      LocPin		      "any"
      cst		      "63"
      modulename	      "h4"
      ppat		      "D:\\altera\\quartus60\\work1\\fir\\DSPBuilder_f"
"irt"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Constant;bwl;8;bwr;"
"0;sat;off;rnd;off;cst;63;LocPin;any;"
    }
    Block {
      BlockType		      Reference
      Name		      "yout"
      Description	      "Sign Binary Fractionnal"
      Ports		      [1, 1]
      Position		      [660, 337, 725, 353]
      ForegroundColor	      "blue"
      SourceBlock	      "bus_alteradspbuilder/AltBus"
      SourceType	      "AltBus AlteraBlockSet"
      sgn		      "Signed Integer"
      nodetype		      "Input Port"
      bwl		      "8"
      bwr		      "0"
      sat		      off
      rnd		      off
      bp		      off
      mask_cst		      "0"
      LocPin		      "any"
      cst		      "0"
      modulename	      "yout"
      ppat		      "D:\\altera\\quartus60\\work1\\fir\\DSPBuilder_f"
"irt"
      nSgCpl		      "1"
      SIGNALCOMPILER_PARAMS   "sgn;Signed Integer;nodetype;Input Port;bwl;8;bw"
"r;0;sat;off;rnd;off;cst;0;LocPin;any;"
    }
    Line {
      SrcBlock		      "h1"
      SrcPort		      1
      Points		      [195, 0]
      DstBlock		      "Product"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Delay1"
      SrcPort		      1
      DstBlock		      "Product3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Delay2"
      SrcPort		      1
      Points		      [15, 0]
      Branch {
	DstBlock		"Product2"
	DstPort			1
      }
      Branch {
	Points			[0, 55; -85, 0]
	DstBlock		"Delay1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Delay"
      SrcPort		      1
      Points		      [30, 0]
      Branch {
	DstBlock		"Product1"
	DstPort			1
      }
      Branch {
	Points			[0, 65; -90, 0]
	DstBlock		"Delay2"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "h2"
      SrcPort		      1
      Points		      [95, 0; 0, -20]
      DstBlock		      "Product1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "h3"
      SrcPort		      1
      Points		      [195, 0]
      DstBlock		      "Product2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "h4"
      SrcPort		      1
      Points		      [95, 0; 0, -10]
      DstBlock		      "Product3"
      DstPort		      2
    }
    Line {
      SrcBlock		      "AltBus"
      SrcPort		      1
      Points		      [30, 0; 0, 50]
      Branch {
	DstBlock		"Delay"
	DstPort			1
      }
      Branch {
	DstBlock		"Product"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Chirp Signal"
      SrcPort		      1
      DstBlock		      "Gain"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Gain"
      SrcPort		      1
      Points		      [0, 45]
      Branch {
	Points			[-60, 0]
	DstBlock		"AltBus"
	DstPort			1
      }
      Branch {
	Points			[480, 0; 0, 235]
	DstBlock		"Scope"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Product"
      SrcPort		      1
      Points		      [35, 0; 0, 120]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Product1"
      SrcPort		      1
      Points		      [20, 0; 0, 15]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Product2"
      SrcPort		      1
      Points		      [30, 0; 0, -85]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Product3"
      SrcPort		      1
      Points		      [25, 0; 0, -200]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      4
    }
    Line {
      SrcBlock		      "Parallel \nAdder Subtractor"
      SrcPort		      1
      DstBlock		      "yout"
      DstPort		      1
    }
    Line {
      SrcBlock		      "yout"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      2
    }
  }
}

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