📄 firtt_dspbuilder_report.html
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<title>SignalCompiler report D:\altera\quartus60\work1\fir\firtt_DspBuilder_Report.html</title>
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<h3> SignalCompiler report </h3>
<i><h5>Use the right-click mouse button to naviguate through firtt_DspBuilder_Report.html
</h5></i><hr><h3>Project Setting</h3><TABLE>
<TR>
<TD><b>Model</b> </TD> <TD> firtt</TD>
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<TD><b>Directory</b> </TD> <TD> D:\altera\quartus60\work1\fir</TD>
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<TD><b>Device family</b> </TD> <TD>Cyclone</TD>
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<TD><b>Synthesis tool</b> </TD> <TD>Quartus II</TD>
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<TD> <b>Optimization </b></TD> <TD>Balanced</TD>
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<TD> <b>Date</b> </TD> <TD>Friday, August 17, 2007</TD>
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<TD> <b>Time</b> </TD> <TD>15:44:03</TD>
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<TD><b>Version</b> </TD> <TD> 6.0 Internal Build 180</TD>
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<h3>Compilation status</h3>
<TABLE>
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<TD>Convert Mdl to VHDL </TD> <TD><b>:</b> PASSED </TD><TD></TD>
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<TD>Synthesis </TD> <TD><b>:</b> --------- </TD><TD></TD>
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<TR> <TD>Quartus II Fitter</TD> <TD><b>:</b> --------- </TD><TD></TD></TR>
</TABLE>
<hr>
<!--<h3>Resource Usage Summary</h3>-->
<!--<h3>Resource Utilization</h3>-->
<!--<h3>Timing Analyzer Summary</h3>-->
<h3>Pin-Out</h3><TABLE>
<TR><TD><b>Pin name </b></TD>
<TD><b>Pin Direction </b></TD>
<TD><b>Bus Type </b></TD></TR>
<TR><TD> clock </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> sclrp </TD><TD> in </TD><TD>std_logic</TD></TR><TR><TD> h1 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h10 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h11 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h12 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h13 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h14 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h15 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h16 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h2 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h3 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h4 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h5 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h6 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h7 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h8 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> h9 </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> xin </TD><TD> </TD><TD> in </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> x16 </TD><TD> out </TD><TD>std_logic_vector(8 downto 0)</TD></TR><TR><TD> yout </TD><TD> </TD><TD> out </TD><TD>std_logic_vector(19 downto 0) )</TD></TR><TR><TD></TR></TABLE><br>
<p><b>Clock input pin (clock):</b>
All registered blocks use the input clock signal <b>'clock'</b>. firtt.mdl does not use PLL.<br><b>Reset input pin (sclrp):</b>
All registered blocks use the global reset input signal <b>'sclrp'</b> , which is synchronous and active high</p><hr>
<h3>Files generated by SignalCompiler</h3><TABLE BORDER>
<TR>
<TD> <b>firtt.vhd</b> </TD><TD>VHDL representation of the design for synthesis and simulation </TD>
</TR>
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<TD> <b>fir4tap4.vhd</b> </TD><TD>VHDL hierarchy for synthesis and simulation </TD>
</TR>
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<TD> <b>fir4tap3.vhd</b> </TD><TD>VHDL hierarchy for synthesis and simulation </TD>
</TR>
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<TD> <b>fir4tap2.vhd</b> </TD><TD>VHDL hierarchy for synthesis and simulation </TD>
</TR>
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<TD> <b>fir4tap1.vhd</b> </TD><TD>VHDL hierarchy for synthesis and simulation </TD>
</TR>
<TR>
</TR>
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<TD> <b>firtt_quartus.tcl</b> </TD><TD>Tcl script for Quartus<font size="-1"><sup>®</font></sup> II compilation. <p><I>When compiling the design manually in the Quartus II software, type </i><b>source firtt_quartus.tcl </b><i> in the Quartus II tcl console (Auxiliary Windows). The Quartus II software executes the Tcl script that sets up the project and environment for your design.</I></p></TD>
</TR>
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<TD> <b>firtt.vec</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II simulation vector file </TD>
</TR>
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<TD> <b>firtt.bsf</b> </TD><TD>Quartus<font size="-1"><sup>®</font></sup> II symbol file</TD>
</TR>
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<TD><b> tb_firtt.vhd</b> </TD><TD>VHDL design testbench for simulation </TD>
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<TD> <b>tb_firtt.tcl</b> </TD><TD>Tcl script for ModelSim simulation <p><I>type </i><b>do tb_firtt.tcl </b><i> at Modelsim prompt.</p></TD>
</TR>
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<TD><b> tb_firtt.v</b> </TD><TD>Verilog design testbench for simulation with Quartus II Verilog Output File (.vo)</TD>
</TR>
</TABLE><br>
<hr>
<h3>Synthesis & compilation log files</h3>
<!--<p><A HREF="firtt.srr">Synplicity Log</A></p>-->
<!--<p><A HREF="exemplar.log">Leonardo Log</A></p>-->
<!--<p><A HREF="firtt.map.rpt">Quartus II Map Log</A></p>-->
<!--<p><A HREF="firtt.fit.rpt">Quartus II Fit Log</A></p>-->
<hr>
<h3>Entity firtt</h3>
<p><A HREF="DSPBuilder_firtt\firttblockInfos.html">Information page</A> on the DSP Builder blocks used in firtt.</p>
<h4>Hierarchy information</h4>
<p>
This section lists the "Hdl Sub-System" block used in the design (Black Box and VHDL)
with the number of instance of those blocks accross the hierarchy branches.
</p>
<TABLE>
<TR>
<TD><a href="#fir4tap1"> fir4tap1 <a></TD> <TD> 4 </TD>
</TR>
</TABLE>
<p><i>VHDL SubSystem </i> :
Each "Hdl Sub-System" map to a unique VHDL entity generated on-the-fly by SignalCompiler, and therefore must
be uniquified in Simulink.
Make sure that "Hdl Sub-System" block with identical names have the
exact same functionality
</p><p><i>Black Box SubSystem</i> :
A Black Box SubSystem is used to import VHDL design into the design using the HDL SubSystem mechanism. SignalCompiler generates only the black component declaration and mapping. For clock signals, SignalCompiler will connect automatically to the global "clock" signal of the design the signal of the black box which has the instance name "simulink_clock"</p>
<h4>Warning Section</h4><p>
<b> Signals Out of Range </b>: This section lists the signals with a bit width greater than 51 bits. Fixed-point DSP Builder models support up to 51 bits of resolution. When the bit width grows over 51 bits, additional VHDL RTL simulations are recommended to estimate the effect of overflow and rounding introduced by double signals.</p><pre>
</pre>
<hr>
<a name="fir4tap4"> </a>
<h3>Entity fir4tap4</h3>
<p><A HREF="DSPBuilder_firtt\fir4tap4blockInfos.html">Information page</A> on the DSP Builder blocks used in fir4tap4.</p>
<hr>
<a name="fir4tap3"> </a>
<h3>Entity fir4tap3</h3>
<p><A HREF="DSPBuilder_firtt\fir4tap3blockInfos.html">Information page</A> on the DSP Builder blocks used in fir4tap3.</p>
<hr>
<a name="fir4tap2"> </a>
<h3>Entity fir4tap2</h3>
<p><A HREF="DSPBuilder_firtt\fir4tap2blockInfos.html">Information page</A> on the DSP Builder blocks used in fir4tap2.</p>
<hr>
<a name="fir4tap1"> </a>
<h3>Entity fir4tap1</h3>
<p><A HREF="DSPBuilder_firtt\fir4tap1blockInfos.html">Information page</A> on the DSP Builder blocks used in fir4tap1.</p>
<hr>
<TABLE><TR><TD align="left"><A HREF="http://www.altera.com/">www.altera.com</A></TD>
<TD> </TD><TD align="right"> <A HREF="d:\altera\DSPBuilder\AltLib\..\doc\ug_dspbuilderTOC.html">help</A></TD>
</TR></TABLE><hr>
DSP Builder <br>Quartus II development tool and MATLAB/Simulink Interface
<br>Version 6.0 Internal Build 180<p> Legal Notice: ⌨️ 快捷键说明
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