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📄 firtt.mdl

📁 是一个基于MATLAB /simulink/DSP BUILDER 的fir数字滤波器的设计
💻 MDL
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      SampleTime	      "-1"
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      "FromPortIcon"
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Arial"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    UseDisplayTextAsClickCallback off
  }
  LineDefaults {
    FontName		    "Arial"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "firtt"
    Location		    [2, 82, 1014, 721]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "Parallel \nAdder Subtractor"
      Ports		      [4, 1]
      Position		      [690, 197, 775, 458]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
      SourceType	      "Sum AlteraBlockSet"
      Inputs		      "4"
      direction		      "+"
      pipeline		      on
      clken		      off
      MaskValue		      "1"
      SIGNALCOMPILER_PARAMS   "clken;off;direction;+;Inputs;4;MaskValue;1;pipe"
"line;on;"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [764, 53, 833, 100]
      ForegroundColor	      "blue"
      SourceBlock	      "Altelink/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Cyclone"
      opt		      "Balanced"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "D:\\altera\\quartus60\\work1\\fir"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    off
      JTAGCable		      "USB-Blaster [USB-0]"
      dspb_ver		      "5.1"
    }
    Block {
      BlockType		      SubSystem
      Name		      "fir4tap1"
      Ports		      [5, 2]
      Position		      [495, 244, 535, 306]
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      MaskHideContents	      off
      MaskType		      "SubSystem AlteraBlockSet"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"fir4tap1"
	Location		[152, 123, 1012, 639]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "x[8:0]"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "h1[8:0]"
	  Position		  [30, 98, 60, 112]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "h2[8:0]"
	  Position		  [30, 198, 60, 212]
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "h4[8:0]"
	  Position		  [30, 328, 60, 342]
	  Port			  "4"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "h5[8:0]"
	  Position		  [35, 423, 65, 437]
	  Port			  "5"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay"
	  Ports			  [1, 1]
	  Position		  [275, 265, 320, 315]
	  ForegroundColor	  "blue"
	  SourceBlock		  "store_alteradspbuilder/Delay"
	  SourceType		  "Delay AlteraBlockSet"
	  depth			  "1"
	  clken			  off
	  MaskValue		  "1"
	  sclr			  off
	  SIGNALCOMPILER_PARAMS	  "depth;1;clken;off;MaskValue;1;sclr;off;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay1"
	  Ports			  [1, 1]
	  Position		  [275, 135, 320, 185]
	  ForegroundColor	  "blue"
	  SourceBlock		  "store_alteradspbuilder/Delay"
	  SourceType		  "Delay AlteraBlockSet"
	  depth			  "1"
	  clken			  off
	  MaskValue		  "1"
	  sclr			  off
	  SIGNALCOMPILER_PARAMS	  "depth;1;clken;off;MaskValue;1;sclr;off;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay2"
	  Ports			  [1, 1]
	  Position		  [275, 25, 320, 75]
	  ForegroundColor	  "blue"
	  SourceBlock		  "store_alteradspbuilder/Delay"
	  SourceType		  "Delay AlteraBlockSet"
	  depth			  "1"
	  clken			  off
	  MaskValue		  "1"
	  sclr			  off
	  SIGNALCOMPILER_PARAMS	  "depth;1;clken;off;MaskValue;1;sclr;off;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Delay3"
	  Ports			  [1, 1]
	  Position		  [275, 365, 320, 415]
	  ForegroundColor	  "blue"
	  SourceBlock		  "store_alteradspbuilder/Delay"
	  SourceType		  "Delay AlteraBlockSet"
	  depth			  "1"
	  clken			  off
	  MaskValue		  "1"
	  sclr			  off
	  SIGNALCOMPILER_PARAMS	  "depth;1;clken;off;MaskValue;1;sclr;off;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Parallel \nAdder Subtractor"
	  Ports			  [4, 1]
	  Position		  [605, 150, 680, 320]
	  ForegroundColor	  "blue"
	  SourceBlock		  "arithm_alteradspbuilder/Parallel \nAdder Su"
"btractor"
	  SourceType		  "Sum AlteraBlockSet"
	  Inputs		  "4"
	  direction		  "+"
	  pipeline		  on
	  clken			  off
	  MaskValue		  "1"
	  SIGNALCOMPILER_PARAMS	  "clken;off;direction;+;Inputs;4;MaskValue;1;"
"pipeline;on;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Product"
	  Ports			  [2, 1]
	  Position		  [390, 148, 455, 197]
	  ForegroundColor	  "blue"
	  SourceBlock		  "arithm_alteradspbuilder/Product"
	  SourceType		  "Product AlteraBlockSet"
	  pipeline		  "2"
	  lpm			  off
	  eab			  off
	  clken			  off
	  MaskValue		  "1"
	  SIGNALCOMPILER_PARAMS	  "clken;off;eab;off;lpm;off;MaskValue;1;pipel"
"ine;2;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Product1"
	  Ports			  [2, 1]
	  Position		  [385, 278, 450, 327]
	  ForegroundColor	  "blue"
	  SourceBlock		  "arithm_alteradspbuilder/Product"
	  SourceType		  "Product AlteraBlockSet"
	  pipeline		  "2"
	  lpm			  off
	  eab			  off
	  clken			  off
	  MaskValue		  "1"
	  SIGNALCOMPILER_PARAMS	  "clken;off;eab;off;lpm;off;MaskValue;1;pipel"
"ine;2;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Product2"
	  Ports			  [2, 1]
	  Position		  [390, 38, 455, 87]
	  ForegroundColor	  "blue"
	  SourceBlock		  "arithm_alteradspbuilder/Product"
	  SourceType		  "Product AlteraBlockSet"
	  pipeline		  "2"
	  lpm			  off
	  eab			  off
	  clken			  off
	  MaskValue		  "1"
	  SIGNALCOMPILER_PARAMS	  "clken;off;eab;off;lpm;off;MaskValue;1;pipel"
"ine;2;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Product3"
	  Ports			  [2, 1]
	  Position		  [385, 378, 450, 427]
	  ForegroundColor	  "blue"
	  SourceBlock		  "arithm_alteradspbuilder/Product"
	  SourceType		  "Product AlteraBlockSet"
	  pipeline		  "2"
	  lpm			  off
	  eab			  off
	  clken			  off
	  MaskValue		  "1"
	  SIGNALCOMPILER_PARAMS	  "clken;off;eab;off;lpm;off;MaskValue;1;pipel"
"ine;2;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "hn1"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 97, 150, 113]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "9"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "hn1"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Input Port;bwl;"
"9;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "hn2"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 197, 150, 213]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "9"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "hn2"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Input Port;bwl;"
"9;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "hn3"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [85, 327, 150, 343]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "9"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "hn3"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Input Port;bwl;"
"9;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "hn4"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [90, 422, 155, 438]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "9"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "hn4"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Input Port;bwl;"
"9;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "xin"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [80, 42, 145, 58]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Input Port"
	  bwl			  "9"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "xin"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Input Port;bwl;"
"9;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "xn4"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [425, 472, 490, 488]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "9"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "xn4"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Output Port;bwl"
";9;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Reference
	  Name			  "yn"
	  Description		  "Sign Binary Fractionnal"
	  Ports			  [1, 1]
	  Position		  [715, 227, 780, 243]
	  ForegroundColor	  "blue"
	  SourceBlock		  "bus_alteradspbuilder/AltBus"
	  SourceType		  "AltBus AlteraBlockSet"
	  sgn			  "Signed Integer"
	  nodetype		  "Output Port"
	  bwl			  "20"
	  bwr			  "0"
	  sat			  off
	  rnd			  off
	  bp			  off
	  mask_cst		  "0"
	  LocPin		  "any"
	  cst			  "0"
	  modulename		  "yn"
	  nSgCpl		  "0"
	  SIGNALCOMPILER_PARAMS	  "sgn;Signed Integer;nodetype;Output Port;bwl"
";20;bwr;0;sat;off;rnd;off;cst;0;LocPin;any;"
	}
	Block {
	  BlockType		  Outport
	  Name			  "y[19:0]"
	  Position		  [805, 228, 835, 242]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "x4[8:0]"
	  Position		  [515, 473, 545, 487]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "Delay2"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Product2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 70; -80, 0]
	    DstBlock		    "Delay1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Delay1"

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