firttaltblk.xml

是一个基于MATLAB /simulink/DSP BUILDER 的fir数字滤波器的设计

            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>fir4tap4</dstblk>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>yout</instancename>
         <sourcename>AltBusAlteraBlockSet</sourcename>
         <instancenumber>19</instancenumber>
         <inport>1</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>sgn</pname>
            <pvalue>SignedInteger</pvalue>
            <pname>nodetype</pname>
            <pvalue>OutputPort</pvalue>
            <pname>bwl</pname>
            <pvalue>20</pvalue>
            <pname>bwr</pname>
            <pvalue>0</pvalue>
            <pname>sat</pname>
            <pvalue>off</pvalue>
            <pname>rnd</pname>
            <pvalue>off</pvalue>
            <pname>cst</pname>
            <pvalue>0</pvalue>
            <pname>LocPin</pname>
            <pvalue>any</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>ParallelAdderSubtractor</srcblk>
            <srcport>1</srcport>
         </port_db>
         <nparameter>9</nparameter>
      </db_block>
      <db_block>
         <instancename>ParallelAdderSubtractor</instancename>
         <sourcename>SumAlteraBlockSet</sourcename>
         <instancenumber>20</instancenumber>
         <inport>4</inport>
         <outport>1</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
            <pname>clken</pname>
            <pvalue>off</pvalue>
            <pname>direction</pname>
            <pvalue>+</pvalue>
            <pname>Inputs</pname>
            <pvalue>4</pvalue>
            <pname>MaskValue</pname>
            <pvalue>1</pvalue>
            <pname>pipeline</pname>
            <pvalue>on</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap4</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap1</srcblk>
            <srcport>1</srcport>
            <inportpos>3</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap2</srcblk>
            <srcport>1</srcport>
            <inportpos>4</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap3</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>yout</dstblk>
         </port_db>
         <nparameter>6</nparameter>
      </db_block>
      <db_block>
         <instancename>fir4tap1</instancename>
         <sourcename>SubSystemAlteraBlockSet</sourcename>
         <instancenumber>21</instancenumber>
         <inport>5</inport>
         <outport>2</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap4</srcblk>
            <srcport>2</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h5</srcblk>
            <srcport>1</srcport>
            <inportpos>3</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h6</srcblk>
            <srcport>1</srcport>
            <inportpos>4</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h7</srcblk>
            <srcport>1</srcport>
            <inportpos>5</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h8</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>2</dstport>
            <dstblk>ParallelAdderSubtractor</dstblk>
            <outportpos>2</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>fir4tap2</dstblk>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
      <db_block>
         <instancename>fir4tap2</instancename>
         <sourcename>SubSystemAlteraBlockSet</sourcename>
         <instancenumber>22</instancenumber>
         <inport>5</inport>
         <outport>2</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap1</srcblk>
            <srcport>2</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h9</srcblk>
            <srcport>1</srcport>
            <inportpos>3</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h10</srcblk>
            <srcport>1</srcport>
            <inportpos>4</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h11</srcblk>
            <srcport>1</srcport>
            <inportpos>5</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h12</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>3</dstport>
            <dstblk>ParallelAdderSubtractor</dstblk>
            <outportpos>2</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>fir4tap3</dstblk>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
      <db_block>
         <instancename>fir4tap3</instancename>
         <sourcename>SubSystemAlteraBlockSet</sourcename>
         <instancenumber>23</instancenumber>
         <inport>5</inport>
         <outport>2</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>fir4tap2</srcblk>
            <srcport>2</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h13</srcblk>
            <srcport>1</srcport>
            <inportpos>3</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h14</srcblk>
            <srcport>1</srcport>
            <inportpos>4</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h15</srcblk>
            <srcport>1</srcport>
            <inportpos>5</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h16</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>4</dstport>
            <dstblk>ParallelAdderSubtractor</dstblk>
            <outportpos>2</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>x16</dstblk>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
      <db_block>
         <instancename>fir4tap4</instancename>
         <sourcename>SubSystemAlteraBlockSet</sourcename>
         <instancenumber>24</instancenumber>
         <inport>5</inport>
         <outport>2</outport>
         <parameters_db>
            <pname>CompiledSampleTime</pname>
            <pvalue>0</pvalue>
         </parameters_db>
         <port_db>
            <inportpos>1</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>xin</srcblk>
            <srcport>1</srcport>
            <inportpos>2</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h1</srcblk>
            <srcport>1</srcport>
            <inportpos>3</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h2</srcblk>
            <srcport>1</srcport>
            <inportpos>4</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h3</srcblk>
            <srcport>1</srcport>
            <inportpos>5</inportpos>
            <inputsignalname></inputsignalname>
            <srcblk>h4</srcblk>
            <srcport>1</srcport>
            <outportpos>1</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>ParallelAdderSubtractor</dstblk>
            <outportpos>2</outportpos>
            <outputsignalname></outputsignalname>
            <outportfanout>1</outportfanout>
            <dstport>1</dstport>
            <dstblk>fir4tap1</dstblk>
         </port_db>
         <nparameter>1</nparameter>
      </db_block>
   </block_dspbuilder>
<top_sources>
	<library></library>
</top_sources>
   <top_subsystem>
      <design_subsystem>fir4tap1</design_subsystem>
      <design_subsystem>fir4tap2</design_subsystem>
      <design_subsystem>fir4tap3</design_subsystem>
      <design_subsystem>fir4tap4</design_subsystem>
   </top_subsystem>
   <top_parameters>
      <starttime>0.0</starttime>
      <stoptime>10</stoptime>
      <fixedstep>auto</fixedstep>
      <nsubsystem>4</nsubsystem>
      <nblocks>24</nblocks>
   </top_parameters>
   <top_signalcompiler>
      <family>Cyclone</family>
      <opt>Balanced</opt>
      <synthtool>Others</synthtool>
      <vstim>on</vstim>
      <SynthAct>None</SynthAct>
      <workdir>D:\altera\quartus60\work1\fir</workdir>
      <Procetype>prod</Procetype>
      <UseReset>on</UseReset>
      <ResetPin>Active High</ResetPin>
      <ClockPin>Output to Pin</ClockPin>
      <ClockPeriod>20</ClockPeriod>
      <UseSignalTap>off</UseSignalTap>
      <CreatePtfFile>off</CreatePtfFile>
      <SignalTapDepth>128</SignalTapDepth>
      <VerilogSupport>off</VerilogSupport>
      <JTAGCable>USB-Blaster [USB-0]</JTAGCable>
      <bContainMegaCoreIpTb>0</bContainMegaCoreIpTb>
   </top_signalcompiler>
</firtt>