main.c

另一个在mpc8272上产生usb sof帧的demo

#include "const_d.h" //   GENERAL CONSTANTS AND DEFINITIONS
#include "mpc8260.h"       /* IMM definitions and declarations */
#include "8270usb.h"       /* USB definitions and declarations */
#include "spr.h"

//#define BASE_ADDR     0x04700000 
#define BASE_ADDR   0x0F000000 // BCSR.cfg

#define BRGCLK 24000000

typedef struct bcsr 
{
	UWORD  bcsr0; /* Board Control and Status Register */
	UWORD  bcsr1;
	UWORD  bcsr2;
	UWORD  bcsr3;

}t_BCSR;
t_BCSR *csr;			  /* Board Control & Status Reg pointer */

typedef struct buffers_descriptor
{
	UHWORD status;
	UHWORD length;
	UWORD  pointer;
}bd ;

#define BASE_EVT 0x0  // Base Address of Exception Vector Table 
#define DEC_INT_VECTOR ((BASE_EVT) + 0x900)  // Base address of decrementer 
#define EXT_INT_VECTOR ((BASE_EVT) + 0x500)  // Base address of external 

#define VECTOR_BLOCK_LEN 0x100

extern UWORD Ex500[];
extern UWORD Ex900[];
t_PQ2IMM  *immr;           /* Internal Memory Map base pointer */

//-------------------------USB
/* USB tokens */
#define IN_TOKEN 0x96
#define OUT_TOKEN 0x87
#define SETUP_TOKEN 0xB4

#define USB_ADR_BD 0x0 //0x0  // offset for address of usb BDs

#define BASE_USB_REGS 0x11B60
#define BASE_USB 0x8B00
#define BASE_USB_ENDPOINTS_PRAM 0x500

t_usb_pram *pram_usb;
usb_regs *reg_usb;
t_usb_endpoint *endp[4];

bd *ep0_txbd[4];
bd *ep0_rxbd[4];  // control

bd *f_txbd[4]; // function
bd *f_rxbd[4];

#define BUF_LEN 0x40
UBYTE ep0_in[4][BUF_LEN];
UBYTE ep0_out[4][BUF_LEN];

UBYTE fep_in[4][BUF_LEN];
UBYTE fep_out[4][BUF_LEN];

UHWORD sl_frame_n;
UBYTE fl_txb, fl_rxb, fl_sof; 
UHWORD max_sof_del;

#define USSFT_OFFSET 0x11B78
UHWORD *ussft;
//=========
UWORD sl1;
//--------------------------------------------------------------------------------
void init_addr(void)
{
    immr = (t_PQ2IMM *)(BASE_ADDR);  /* pointer to MPC8260 internal memory map. */
	reg_usb = (usb_regs *)(BASE_ADDR+BASE_USB_REGS);
	ussft=(UHWORD *)(BASE_ADDR+USSFT_OFFSET);

    csr = (t_BCSR *)(immr->memc_regs[1].br & 0xFFFF8000);
}
//-----------------------end init_addr----------------------------------------------
UWORD calc_brg(UWORD BRG_CLK, UWORD CLK)
{
UWORD clock_div, div16, res;
    div16=0;
    clock_div=(BRG_CLK/CLK)-1;
    if (clock_div>4095) 
    {
       div16=1;
       clock_div=(BRG_CLK/CLK/16)-1;
    }
    clock_div <<= 1;
    res=W15+clock_div+div16;
    return(res);
} 
//--------------------------------end calc_brg--------------------------------
#define PortA 0
#define PortB 1
#define PortC 2
#define PortD 3
void usb_pin_assignment_8272(void)
{
	immr->io_regs[PortD].ppar |= W25;
	immr->io_regs[PortD].psor &=~W25;
	immr->io_regs[PortD].pdir &=~W25;  // USBRXD to PD25; P1_A7
	immr->io_regs[PortD].podr &=~W25;  

	immr->io_regs[PortC].ppar |= W11;
	immr->io_regs[PortC].psor &=~W11;
	immr->io_regs[PortC].pdir &=~W11;  // USBRxP to PC11; P1_D21
	immr->io_regs[PortC].podr &=~W11;

	immr->io_regs[PortC].ppar |= W10;
	immr->io_regs[PortC].psor &=~W10;
	immr->io_regs[PortC].pdir &=~W10;  // USBRxN to PC10; P1_D24
	immr->io_regs[PortC].podr &=~W10;

	immr->io_regs[PortD].ppar |= W23;
	immr->io_regs[PortD].psor &=~W23;
	immr->io_regs[PortD].pdir |= W23;  // USBTxP to PD23; P1_A9
	immr->io_regs[PortD].podr &=~W23;  

	immr->io_regs[PortD].ppar |= W24;
	immr->io_regs[PortD].psor &=~W24;
	immr->io_regs[PortD].pdir |= W24;  // USBTxN to PD24; P1_A8
	immr->io_regs[PortD].podr &=~W24;  

	immr->io_regs[PortC].ppar |= W20;
	immr->io_regs[PortC].psor &=~W20;
	immr->io_regs[PortC].pdir |= W20;  // USBOE to PC20; P1_D12
	immr->io_regs[PortC].podr &=~W20;
}
//-----------------------------end usb_pin_assignment_8272----------------------------------------------------
void usb_clk_assignment_8272(void)
{
/*
immr->brgs_brgc1 =calc_brg(BRGCLK, 6000000);  // enabled CLK
immr->cpm_mux_cmxscr &=~(W21 | W22 | W23); // BRG1 to TX SCC4 (USB clock)
*/
	immr->io_regs[PortC].ppar |= W24;
	immr->io_regs[PortC].psor &=~W24;
	immr->io_regs[PortC].pdir &=~W24;  // CLK8/TIN4 to PC24; P1_D8

	immr->cpm_mux_cmxscr |= (W21 | W22 | W23); // SCC3 transmit/USB clock is clk8

}
//------------------------end usb_clk_assignment_8272-------------------
#define USB_STOP_TX 0x2E60000A // to register CPCR
#define USB_RESTART_TX 0x2E60000B // to register CPCR
void cpm_reset(void)
{
	immr->cpm_cpcr=(UWORD)(W0+W15); 
	while(immr->cpm_cpcr & W15) {}           // wait
}
//------------------------end cpm_reset-------------------
void usb_stop(UBYTE n_ep)
{
	immr->cpm_cpcr=(UWORD)(USB_STOP_TX+(n_ep << 4)+W15); 
	while(immr->cpm_cpcr & W15) {}           // wait
}
//------------------------end usb_stop-------------------
void usb_restart(UBYTE n_ep)
{
	immr->cpm_cpcr=(UWORD)(USB_RESTART_TX+(n_ep << 4)+W15); 
	while(immr->cpm_cpcr & W15) {}           // wait
}
//------------------------end usb_stop-------------------
void flush_restart_ep(UBYTE n_ep)
{
	immr->cpm_cpcr=(UWORD)(USB_STOP_TX+(n_ep << 4)+W15); // stop
	while(immr->cpm_cpcr & W15) {}           // wait
	reg_usb->uscom=(UBYTE)(n_ep | 0x40);
	immr->cpm_cpcr=(UWORD)(USB_RESTART_TX+(n_ep << 4)+W15); // restart
	while(immr->cpm_cpcr & W15) {}           // wait
}
//-------------------end flush_restart_ep-----------------------
void init_usb_host(void)
{
UWORD j,l;
	usb_pin_assignment_8272();
	usb_clk_assignment_8272();

	pram_usb = (t_usb_pram *)(BASE_ADDR +BASE_USB);
	j = BASE_ADDR + USB_ADR_BD;
// control point
	for (l=0; l<4; l++) { ep0_rxbd[l]=(bd *)j; j +=8; }         // 8 is SIZE of BD 
	for (l=0; l<4; l++) { ep0_txbd[l]=(bd *)j; j +=8; }         // 8 is SIZE of BD 
// other point
	for (l=0; l<4; l++) { f_rxbd[l]=(bd *)j; j +=8; }         // 8 is SIZE of BD 
	for (l=0; l<4; l++) { f_txbd[l]=(bd *)j; j +=8; }			// 8 is SIZE of BD 

	j = BASE_ADDR + BASE_USB_ENDPOINTS_PRAM;
	for (l=0; l<4; l++) { endp[l]=(t_usb_endpoint *)j; j +=0x20; }			// 0x20 is SIZE of Endpoint Parameter Block
	for (l=0; l<4; l++) pram_usb->ep_ptr[l]=(UHWORD)endp[l];
	pram_usb->rstate=0;
	pram_usb->frame_n=0;
// control
		endp[0]->rbase=(UHWORD)&(ep0_rxbd[0]->status);
		endp[0]->tbase=(UHWORD)&(ep0_txbd[0]->status);
		endp[0]->rfcr=0x18;
		endp[0]->tfcr=0x18;
		endp[0]->mrblr=0x80;
		endp[0]->rbptr=(UHWORD)&(ep0_rxbd[0]->status);
		endp[0]->tbptr=(UHWORD)&(ep0_txbd[0]->status);
		endp[0]->tstate=0;
		endp[0]->himmmr=BASE_ADDR >> 16;
// Other points	
	for (l=1; l<4; l++)
	{
		endp[l]->rbase=(UHWORD)&(f_rxbd[l]->status);
		endp[l]->tbase=(UHWORD)&(f_txbd[l]->status);
		endp[l]->rfcr=0x18;
		endp[l]->tfcr=0x18;
		endp[l]->mrblr=0x80;
		endp[l]->rbptr=(UHWORD)&(f_rxbd[l]->status);
		endp[l]->tbptr=(UHWORD)&(f_txbd[l]->status);
		endp[l]->tstate=0;
		endp[l]->himmmr=BASE_ADDR >> 16;
	}

	reg_usb->usep[0]=0x0020;  // RTE is cleared
	reg_usb->usep[1]=0x1200;  // EP1
//reg_usb->usep[1]=0x1000;  // EP1
	reg_usb->usmod=6;  // 
//reg_usb->usmod=2;  // 

	reg_usb->usadr=5;

	for (l=0; l<4; l++) 
	{ 
		ep0_txbd[l]->pointer=(UWORD )&ep0_out[l][0];
		ep0_txbd[l]->length=10; 
		ep0_txbd[l]->status=HW2; 
		
		ep0_rxbd[l]->pointer=(UWORD )&ep0_in[l][0];
		ep0_rxbd[l]->length=0; 
		ep0_rxbd[l]->status=HW2; 
	}
	for (l=1; l<4; l++) 
	{ 
		f_txbd[l]->pointer=(UWORD )&fep_out[l][0];
		f_txbd[l]->length=10; 
		f_txbd[l]->status=HW2; 
		
		f_rxbd[l]->pointer=(UWORD )&fep_in[l][0];
		f_rxbd[l]->length=0; 
		f_rxbd[l]->status=HW2; 
	}

	reg_usb->usber = 0xffff;
	reg_usb->usmod |=1;
}
//---------------------end init_usb_host---------------------------------------------------------
void enable_sof_generation(void)
{
	reg_usb->usmod &=~1; // disable USB
	reg_usb->usmod |=8; // enable SOF generation
	immr->cpm_rccr 		 |= 0x00080000;
	reg_usb->usmod |=1;
}
//----------end enable_sof_generation--------------------------
// len-bit I/O -- input byte:  MSB..LSB;   return byte: LSB..MSB
// 8 >= len >= 0
UBYTE reverse8(UBYTE input, UBYTE len)
{
int i;
UBYTE the_reverse = 0;
UBYTE the_bit;
    for(i=0;i<len;i++)
    {
        the_bit = ((input & (1<<i)) != 0);
        the_reverse |= the_bit << ((len-1) - i);
    }
    return the_reverse;