📄 test8key3.lst
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(0449) mov reg[INT_MSK0],0
0110: 62 E0 00 MOV REG[224],0
(0450)
(0451) ; Everything has started OK. Now select requested CPU & sleep frequency.
(0452) ;
(0453) M8C_SetBank1
0113: 71 10 OR F,16
(0454) mov reg[OSC_CR0],(SLEEP_TIMER_JUST | CPU_CLOCK_JUST)
0115: 62 E0 00 MOV REG[224],0
(0455) M8C_SetBank0
0118: 70 EF AND F,239
(0456)
(0457) ; Global Interrupt are NOT enabled, this should be done in main().
(0458) ; LVD is set but will not occur unless Global Interrupts are enabled.
(0459) ; Global Interrupts should be enabled as soon as possible in main().
(0460) ;
(0461) mov reg[INT_VC],0 ; Clear any pending interrupts which may
011A: 62 E2 00 MOV REG[226],0
(0462) ; have been set during the boot process.
(0463) IF ENABLE_LJMP_TO_MAIN
(0464) ljmp _main ; goto main (no return)
(0465) ELSE
(0466) lcall _main ; call main
011D: 7C 0B 8D LCALL _main
(0467) .Exit:
(0468) jmp .Exit ; Wait here after return till power-off or reset
0120: 8F FF JMP 0x0120
(0469) ENDIF
(0470)
(0471) ;---------------------------------
(0472) ; Library Access to Global Parms
(0473) ;---------------------------------
(0474) ;
(0475) bGetPowerSetting:
(0476) _bGetPowerSetting:
(0477) ; Returns value of POWER_SETTING in the A register.
(0478) ; No inputs. No Side Effects.
(0479) ;
(0480) IF (POWER_SETTING & POWER_SET_2V7)
(0481) mov A, POWER_SETTING | POWER_SET_SLOW_IMO
(0482) ELSE
(0483) mov A, POWER_SETTING ; Supply voltage and internal main osc
0122: 50 10 MOV A,16
(0484) ENDIF
(0485) ret
0124: 7F RET
0125: 30 HALT
0126: 30 HALT
0127: 30 HALT
0128: 30 HALT
0129: 30 HALT
012A: 30 HALT
012B: 30 HALT
012C: 30 HALT
012D: 30 HALT
012E: 30 HALT
012F: 30 HALT
0130: 30 HALT
0131: 30 HALT
0132: 30 HALT
0133: 30 HALT
0134: 30 HALT
0135: 30 HALT
0136: 30 HALT
0137: 30 HALT
0138: 30 HALT
0139: 30 HALT
013A: 30 HALT
013B: 30 HALT
013C: 30 HALT
013D: 30 HALT
013E: 30 HALT
013F: 30 HALT
0140: 30 HALT
0141: 30 HALT
0142: 30 HALT
0143: 30 HALT
0144: 30 HALT
0145: 30 HALT
0146: 30 HALT
0147: 30 HALT
0148: 30 HALT
0149: 30 HALT
014A: 30 HALT
014B: 30 HALT
014C: 30 HALT
014D: 30 HALT
014E: 30 HALT
014F: 30 HALT
0150: 2D 20 OR [X+32],A
0152: 20 POP X
0153: 20 POP X
0154: 20 POP X
0155: 42 72 69 AND REG[X+114],105
0158: 67 ASR A
0159: 68 74 ASR [116]
015B: 20 POP X
015C: 20 POP X
015D: 20 POP X
015E: 20 POP X
015F: 2B 00 OR A,[X+0]
0161: 2D 20 OR [X+32],A
0163: 20 POP X
0164: 20 POP X
0165: 20 POP X
0166: 56 6F 6C MOV [X+111],108
0169: 75 INC X
016A: 6D RRC A
016B: 65 20 ASL [32]
016D: 20 POP X
016E: 20 POP X
016F: 20 POP X
0170: 2B 00 OR A,[X+0]
0172: 2D 20 OR [X+32],A
0174: 20 POP X
0175: 20 POP X
0176: 20 POP X
0177: 43 68 61 OR REG[104],97
017A: 6E 6E RRC [110]
017C: 65 6C ASL [108]
017E: 20 POP X
017F: 20 POP X
0180: 20 POP X
0181: 2B 00 OR A,[X+0]
0183: 50 54 MOV A,84
0185: 43 43 20 OR REG[67],32
0188: 20 POP X
0189: 20 POP X
018A: 20 POP X
018B: 20 POP X
018C: 20 POP X
018D: 20 POP X
018E: 00 SWI
018F: 50 53 MOV A,83
0191: 6F 43 RRC [X+67]
0193: 20 POP X
0194: 43 61 70 OR REG[97],112
0197: 53 65 MOV [101],A
0199: 6E 63 RRC [99]
019B: 65 20 ASL [32]
019D: 20 POP X
019E: 00 SWI
019F: 0D 67 ADC [X+103],A
FILE: lib\psocconfigtbl.asm
(0001) ; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
(0002) ;
(0003) include "m8c.inc"
(0004) ; Personalization tables
(0005) export LoadConfigTBL_test8key3
(0006) AREA psoc_config(rom, rel)
(0007) LoadConfigTBL_test8key3:
(0008) ; Ordered Global Register values
(0009) M8C_SetBank1
01A1: 71 10 OR F,16
(0010) mov reg[00h], 00h ; Port_0_DriveMode_0 register (PRT0DM0)
01A3: 62 00 00 MOV REG[0],0
(0011) mov reg[01h], ffh ; Port_0_DriveMode_1 register (PRT0DM1)
01A6: 62 01 FF MOV REG[1],255
(0012) M8C_SetBank0
01A9: 70 EF AND F,239
(0013) mov reg[03h], ffh ; Port_0_DriveMode_2 register (PRT0DM2)
01AB: 62 03 FF MOV REG[3],255
(0014) mov reg[02h], 00h ; Port_0_GlobalSelect register (PRT0GS)
01AE: 62 02 00 MOV REG[2],0
(0015) M8C_SetBank1
01B1: 71 10 OR F,16
(0016) mov reg[02h], 00h ; Port_0_IntCtrl_0 register (PRT0IC0)
01B3: 62 02 00 MOV REG[2],0
(0017) mov reg[03h], 00h ; Port_0_IntCtrl_1 register (PRT0IC1)
01B6: 62 03 00 MOV REG[3],0
(0018) M8C_SetBank0
01B9: 70 EF AND F,239
(0019) mov reg[01h], 00h ; Port_0_IntEn register (PRT0IE)
01BB: 62 01 00 MOV REG[1],0
(0020) M8C_SetBank1
01BE: 71 10 OR F,16
(0021) mov reg[04h], 00h ; Port_1_DriveMode_0 register (PRT1DM0)
01C0: 62 04 00 MOV REG[4],0
(0022) mov reg[05h], ffh ; Port_1_DriveMode_1 register (PRT1DM1)
01C3: 62 05 FF MOV REG[5],255
(0023) M8C_SetBank0
01C6: 70 EF AND F,239
(0024) mov reg[07h], ffh ; Port_1_DriveMode_2 register (PRT1DM2)
01C8: 62 07 FF MOV REG[7],255
(0025) mov reg[06h], 00h ; Port_1_GlobalSelect register (PRT1GS)
01CB: 62 06 00 MOV REG[6],0
(0026) M8C_SetBank1
01CE: 71 10 OR F,16
(0027) mov reg[06h], 00h ; Port_1_IntCtrl_0 register (PRT1IC0)
01D0: 62 06 00 MOV REG[6],0
(0028) mov reg[07h], 00h ; Port_1_IntCtrl_1 register (PRT1IC1)
01D3: 62 07 00 MOV REG[7],0
(0029) M8C_SetBank0
01D6: 70 EF AND F,239
(0030) mov reg[05h], 00h ; Port_1_IntEn register (PRT1IE)
01D8: 62 05 00 MOV REG[5],0
(0031) M8C_SetBank1
01DB: 71 10 OR F,16
(0032) mov reg[08h], 7fh ; Port_2_DriveMode_0 register (PRT2DM0)
01DD: 62 08 7F MOV REG[8],127
(0033) mov reg[09h], 80h ; Port_2_DriveMode_1 register (PRT2DM1)
01E0: 62 09 80 MOV REG[9],128
(0034) M8C_SetBank0
01E3: 70 EF AND F,239
(0035) mov reg[0bh], 80h ; Port_2_DriveMode_2 register (PRT2DM2)
01E5: 62 0B 80 MOV REG[11],128
(0036) mov reg[0ah], 00h ; Port_2_GlobalSelect register (PRT2GS)
01E8: 62 0A 00 MOV REG[10],0
(0037) M8C_SetBank1
01EB: 71 10 OR F,16
(0038) mov reg[0ah], 00h ; Port_2_IntCtrl_0 register (PRT2IC0)
01ED: 62 0A 00 MOV REG[10],0
(0039) mov reg[0bh], 00h ; Port_2_IntCtrl_1 register (PRT2IC1)
01F0: 62 0B 00 MOV REG[11],0
(0040) M8C_SetBank0
01F3: 70 EF AND F,239
(0041) mov reg[09h], 00h ; Port_2_IntEn register (PRT2IE)
01F5: 62 09 00 MOV REG[9],0
(0042) M8C_SetBank1
01F8: 71 10 OR F,16
(0043) mov reg[0ch], 00h ; Port_3_DriveMode_0 register (PRT3DM0)
01FA: 62 0C 00 MOV REG[12],0
(0044) mov reg[0dh], 00h ; Port_3_DriveMode_1 register (PRT3DM1)
01FD: 62 0D 00 MOV REG[13],0
(0045) M8C_SetBank0
0200: 70 EF AND F,239
(0046) mov reg[0fh], 00h ; Port_3_DriveMode_2 register (PRT3DM2)
0202: 62 0F 00 MOV REG[15],0
(0047) mov reg[0eh], 00h ; Port_3_GlobalSelect register (PRT3GS)
0205: 62 0E 00 MOV REG[14],0
(0048) M8C_SetBank1
0208: 71 10 OR F,16
(0049) mov reg[0eh], 00h ; Port_3_IntCtrl_0 register (PRT3IC0)
020A: 62 0E 00 MOV REG[14],0
(0050) mov reg[0fh], 00h ; Port_3_IntCtrl_1 register (PRT3IC1)
020D: 62 0F 00 MOV REG[15],0
(0051) M8C_SetBank0
0210: 70 EF AND F,239
(0052) mov reg[0dh], 00h ; Port_3_IntEn register (PRT3IE)
0212: 62 0D 00 MOV REG[13],0
(0053) M8C_SetBank0
0215: 70 EF AND F,239
(0054) ; Global Register values
(0055) mov reg[60h], 09h ; AnalogColumnInputSelect register (AMX_IN)
0217: 62 60 09 MOV REG[96],9
(0056) mov reg[64h], 00h ; AnalogComparatorControl0 register (CMP_CR0)
021A: 62 64 00 MOV REG[100],0
(0057) mov reg[66h], 00h ; AnalogComparatorControl1 register (CMP_CR1)
021D: 62 66 00 MOV REG[102],0
(0058) mov reg[61h], 00h ; AnalogMuxBusConfig register (AMUXCFG)
0220: 62 61 00 MOV REG[97],0
(0059) mov reg[e6h], 10h ; DecimatorControl_0 register (DEC_CR0)
0223: 62 E6 10 MOV REG[230],16
(0060) mov reg[e7h], 00h ; DecimatorControl_1 register (DEC_CR1)
0226: 62 E7 00 MOV REG[231],0
(0061) mov reg[d6h], 00h ; I2CConfig register (I2CCFG)
0229: 62 D6 00 MOV REG[214],0
(0062) mov reg[62h], 00h ; PWM_Control register (PWM_CR)
022C: 62 62 00 MOV REG[98],0
(0063) mov reg[b0h], 03h ; Row_0_InputMux register (RDI0RI)
022F: 62 B0 03 MOV REG[176],3
(0064) mov reg[b1h], 00h ; Row_0_InputSync register (RDI0SYN)
0232: 62 B1 00 MOV REG[177],0
(0065) mov reg[b2h], 00h ; Row_0_LogicInputAMux register (RDI0IS)
0235: 62 B2 00 MOV REG[178],0
(0066) mov reg[b3h], 33h ; Row_0_LogicSelect_0 register (RDI0LT0)
0238: 62 B3 33 MOV REG[179],51
(0067) mov reg[b4h], 33h ; Row_0_LogicSelect_1 register (RDI0LT1)
023B: 62 B4 33 MOV REG[180],51
(0068) mov reg[b5h], 00h ; Row_0_OutputDrive_0 register (RDI0SRO0)
023E: 62 B5 00 MOV REG[181],0
(0069) mov reg[b6h], 00h ; Row_0_OutputDrive_1 register (RDI0SRO1)
0241: 62 B6 00 MOV REG[182],0
(0070) ; Instance name CSR_1, User Module CSR
(0071) ; Instance name CSR_1, Block Name CMP(ACE00)
(0072) mov reg[72h], 4fh ;CSR_1_ACE_CONTROL1_REG(ACE00CR1)
0244: 62 72 4F MOV REG[114],79
(0073) mov reg[73h], 00h ;CSR_1_ACE_CONTROL2_REG(ACE00CR2)
0247: 62 73 00 MOV REG[115],0
(0074) ; Instance name CSR_1, Block Name Counter16_LSB(DBB01)
(0075) mov reg[27h], 02h ;CSR_1_CTR_CONTROL_LSB_REG(DBB01CR0)
024A: 62 27 02 MOV REG[39],2
(0076) mov reg[25h], 00h ;CSR_1_CTR_PERIOD_LSB_REG(DBB01DR1)
024D: 62 25 00 MOV REG[37],0
(0077) mov reg[26h], 00h ;CSR_1_CTR_COMPARE_LSB_REG(DBB01DR2)
0250: 62 26 00 MOV REG[38],0
(0078) ; Instance name CSR_1, Block Name Counter16_MSB(DCB02)
(0079) mov reg[2bh], 00h ;CSR_1_CTR_CONTROL_MSB_REG(DCB02CR0)
0253: 62 2B 00 MOV REG[43],0
(0080) mov reg[29h], 00h ;CSR_1_CTR_PERIOD_MSB_REG(DCB02DR1)
0256: 62 29 00 MOV REG[41],0
(0081) mov reg[2ah], 00h ;CSR_1_CTR_COMPARE_MSB_REG(DCB02DR2)
0259: 62 2A 00 MOV REG[42],0
(0082) ; Instance name CSR_1, Block Name PWM(DBB00)
(0083) mov reg[23h], 00h ;CSR_1_PWM_CONTROL_REG(DBB00CR0)
025C: 62 23 00 MOV REG[35],0
(0084) mov reg[21h], 00h ;CSR_1_PWM_PERIOD_REG(DBB00DR1)
025F: 62 21 00 MOV REG[33],0
(0085) mov reg[22h], 00h ;CSR_1_PWM_COMPARE_REG(DBB00DR2)
0262: 62 22 00 MOV REG[34],0
(0086) ; Instance name LCD_1, User Module LCD
(0087) M8C_SetBank1
0265: 71 10 OR F,16
(0088) ; Global Register values
(0089) mov reg[61h], 00h ; AnalogClockSelect1 register (CLK_CR1)
0267: 62 61 00 MOV REG[97],0
(0090) mov reg[60h], 00h ; AnalogColumnClockSelect register (CLK_CR0)
026A: 62 60 00 MOV REG[96],0
(0091) mov reg[62h], 00h ; AnalogIOControl_0 register (ABF_CR0)
026D: 62 62 00 MOV REG[98],0
(0092) mov reg[67h], 33h ; AnalogLUTControl0 register (ALT_CR0)
0270: 62 67 33 MOV REG[103],51
(0093) mov reg[64h], 00h ; ComparatorGlobalOutEn register (CMP_GO_EN)
0273: 62 64 00 MOV REG[100],0
(0094) mov reg[fdh], 00h ; DAC_Control register (DAC_CR)
0276: 62 FD 00 MOV REG[253],0
(0095) mov reg[d1h], 00h ; GlobalDigitalInterconnect_Drive_Even_Input register (GDI_E_IN)
0279: 62 D1 00 MOV REG[209],0
(0096) mov reg[d3h], 00h ; GlobalDigitalInterconnect_Drive_Even_Output register (GDI_E_OU)
027C: 62 D3 00 MOV REG[211],0
(0097) mov reg[d0h], 00h ; GlobalDigitalInterconnect_Drive_Odd_Input register (GDI_O_IN)
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