📄 csr_1.lis
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; Insert your custom declarations above this banner
;---------------------------------------------------
;@PSoC_UserCode_END@ (Do not change this line.)
;------------------------
; Constant Definitions
;------------------------
AREA UserModules (ROM, REL, CON)
0001 LSB: equ 1
0000 MSB: equ 0
0000
0000 ;---------------------------------
0000 ; Tables below generated by Wizard
0000 ;---------------------------------
0000
0000 ; The Switch Table consist of two bytes for each switch. The first byte is the
0000 ; port number and the second is the bit mask for the bit. (Not the bit number)
0000 ; For example an entry for port 2 bit 3 (P2[3]) would be "dw 0x0208"
0000 ;
0000 ; This table consist of 0xb switches.
0000 CSR_1_Switch_Table:
0000 _CSR_1_Switch_Table:
0000 0104 dw 0x0104 // Port 1 Bit 2
0002 0110 dw 0x0110 // Port 1 Bit 4
0004 0140 dw 0x0140 // Port 1 Bit 6
0006 0001 dw 0x0001 // Port 0 Bit 0
0008 0002 dw 0x0002 // Port 0 Bit 1
000A 0004 dw 0x0004 // Port 0 Bit 2
000C 0008 dw 0x0008 // Port 0 Bit 3
000E 0010 dw 0x0010 // Port 0 Bit 4
0010 0020 dw 0x0020 // Port 0 Bit 5
0012 0040 dw 0x0040 // Port 0 Bit 6
0014 0080 dw 0x0080 // Port 0 Bit 7
0016
0016
0016 .SECTION
0016 ;-----------------------------------------------------------------------------
0016 ; FUNCTION NAME: CSR_1_Start(void)
0016 ;
0016 ; DESCRIPTION:
0016 ; Initializes registers and turns on the comparitor.
0016 ;
0016 ;-----------------------------------------------------------------------------
0016 ;
0016 ; ARGUMENTS:
0016 ; None
0016 ;
0016 ; RETURNS: None.
0016 ; SIDE EFFECTS:
0016 ; The A and X registers may be modified by this or future implementations
0016 ; of this function. The same is true for all RAM page pointer registers in
0016 ; the Large Memory Model. When necessary, it is the calling function's
0016 ; responsibility to perserve their values across calls to fastcall16
0016 ; functions.
0016 ;
0016 CSR_1_Start:
0016 _CSR_1_Start:
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
IF ( SYSTEM_LARGE_MEMORY_MODEL )
0016 62D01B mov reg[CUR_PP], >CSR_1_bPWMPeriod
ENDIF
IF (CSR_1_Method)
// Period Method
mov [CSR_1_bPWMPeriod], 0x10
mov reg[CSR_1_PWM_PERIOD_REG],0x10 ; Set period (default to 10 cycles)
mov reg[CSR_1_PWM_COMPARE_REG],0x0E ; Set compare
mov reg[DAC_D], 0x80 ; Set Dac at medium level
ELSE
// Frequency Method
0019 551BFF mov [CSR_1_bPWMPeriod], 0xFF
001C 6221FF mov reg[CSR_1_PWM_PERIOD_REG],0xFF ; Set period
001F 6222FD mov reg[CSR_1_PWM_COMPARE_REG],0xFD ; Set compare
0022 62FD80 mov reg[DAC_D], 0x80 ; Set Dac at medium level
ENDIF
0025 626600 mov reg[CMP_CR1],0x00 ; CLDIS0 - synced comparator input enters mux
0028
0028 62E600 mov reg[DEC_CR0],0x00 ; IGEN0 - output of comparator is not ANDed with a PWM
002B
002B 43B003 or reg[RDI0RI],0x03 ; Connect Row 0 to GIO0[4]
002E
002E
002E 7110 or F, FLAG_XIO_MASK
0030 62FD03 mov reg[DAC_CR],0x03 ; Range high = 0x08, Reset on G00[4] = 0x02, Dac Enable = 0x01
0033 626408 mov reg[CMP_GO_EN],0x08 ; GOO[4] out = 0x08, SEL0 - now sends output of IGEN0
0036 43D210 or reg[GDI_O_OU],0x10 ; THIS SHOULD WORK IN THE XML DEBUG
0039
0039 62D800 mov reg[MUX_CR0],0x00 ; Make sure all switches are off by default
003C 62D900 mov reg[MUX_CR1],0x00
003F 62DA00 mov reg[MUX_CR2],0x00
0042 62DB00 mov reg[MUX_CR3],0x00
0045
0045 436B04 or reg[CLK_CR3],0x04 ; Use Sysclock direct for Column 0
0048
0048 62223C mov reg[CSR_1_PWM_OUT_REG],0x3C ; Output PWM compare to row 0, TC to row 3
004B
IF (CSR_1_Method)
// Period Method
mov reg[CSR_1_PWM_IN_REG],0x1C ; Data = 0x10 (High) and Clock = 0x0C (Row_Input_0)
mov reg[CSR_1_CTR_INPUT_LSB_REG],0xFC ; Data = 0xF0 (Row_input_3) and Clock = 0x0X (SysClk direct see output reg)
mov reg[CSR_1_CTR_INPUT_MSB_REG],0x3C ; Data = 0x30 (Chain from LSB) and Clock = 0x0C (SysClk direct see output reg)
mov reg[CSR_1_CTR_OUTPUT_LSB_REG],0xC0 ; Use SysClk direct
mov reg[CSR_1_CTR_OUTPUT_MSB_REG],0xC0 ; Use SysClk direct
ELSE
// Frequency Method
004B 62DE00 mov reg[OSC_CR4],0x00 ; Use Sysclock as input to VC3
004E 62DFFF mov reg[OSC_CR3],0xFF ; Set VC3 to 255
0051 622111 mov reg[CSR_1_PWM_IN_REG],0x11 ; Data = 0x10 (High) and Clock = 0x01 (VC3)
0054 6225FC mov reg[CSR_1_CTR_INPUT_LSB_REG],0xFC ; Data = 0x80 (Row_input_3) and Clock = 0x0C (Row_Input_0)
0057 62293C mov reg[CSR_1_CTR_INPUT_MSB_REG],0x3C ; Data = 0x30 (Chain from LSB) and Clock = 0x0C (Row_Input_0)
005A 622600 mov reg[CSR_1_CTR_OUTPUT_LSB_REG],0x00 ; Sync to SysClk and no outputs
005D 622A00 mov reg[CSR_1_CTR_OUTPUT_MSB_REG],0x00 ; Sync to SysClk and no outputs
0060
ENDIF
0060 41B27F and reg[RDI0IS], ~0x80 ; Make sure input 'A' to LUT3 is RO[3]
0063 41B40F and reg[RDI0LT1],~0xF0
0066 43B440 or reg[RDI0LT1],0x40 ; Combine PWM compare and ~PWM TC running to GPIO: ~A&B (LUT3)
0069 41B60F and reg[RDI0RO1],~0xF0
006C 43B680 or reg[RDI0RO1],0x80 ; Output LUT3 to global out odd 7
006F 43D280 or reg[GDI_O_OU],0x80 ; Drive global out odd 7 onto global in odd 7
0072 43B0C0 or reg[RDI0RI],0xC0 ; Row input 3 comes from global in odd 7
0075 41B1F7 and reg[RDI0SYN],~0x08 ; Row input 3 passes with synchronization
0078
0078 70EF and F, ~FLAG_XIO_MASK
007A
007A 9001 call CSR_1_ClearSwitches ; Loop through all keys and deactivate
007C ; This also puts pin in proper mode.
007C
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_2
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_3 )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
IF ( SYSTEM_IDXPG_TRACKS_STK_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_11b
ENDIF
ENDIF ; PGMODE LOCKED
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
and F, ~FLAG_PGMODE_MASK ; NOTE: transition thru 00b state
or F, FLAG_PGMODE_MASK & FLAG_PGMODE_10b
ENDIF
ENDIF ; PGMODE FREE
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF ; RAM_USE_CLASS_3
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_4 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_4
007C 7F ret
007D .ENDSECTION
007D
007D
007D
007D
007D .SECTION
007D ;-----------------------------------------------------------------------------
007D ; FUNCTION NAME: CSR_1_ClearSwitches(void)
007D ;
007D ; DESCRIPTION:
007D ; Clears all switche⌨️ 快捷键说明
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