📄 freq_occur_ad_to_pwm.lst
字号:
02B7: 7F RET
(0063)
(0064) ;---------------------------------------------------------------------------
(0065) ; Load Configuration freq_occur_ad_to_pwm
(0066) ;
(0067) ; Load configuration registers for freq_occur_ad_to_pwm.
(0068) ; IO Bank 0 registers a loaded first,then those in IO Bank 1.
(0069) ;
(0070) ; INPUTS: None.
(0071) ; RETURNS: Nothing.
(0072) ; SIDE EFFECTS: Registers are volatile: the CPU A and X registers may be
(0073) ; modified as may the Page Pointer registers!
(0074) ; In the large memory model currently only the page
(0075) ; pointer registers listed below are modified. This does
(0076) ; not guarantee that in future implementations of this
(0077) ; function other page pointer registers will not be
(0078) ; modified.
(0079) ;
(0080) ; Page Pointer Registers Modified:
(0081) ; CUR_PP
(0082) ;
(0083) _LoadConfig_freq_occur_ad_to_pwm:
(0084) LoadConfig_freq_occur_ad_to_pwm:
(0085) RAM_PROLOGUE RAM_USE_CLASS_4
(0086)
(0087) push x
02B8: 10 PUSH X
(0088) M8C_SetBank0 ; Force bank 0
02B9: 70 EF AND F,239
(0089) mov a, 0 ; Specify bank 0
02BB: 50 00 MOV A,0
(0090) asr a ; Store in carry flag
02BD: 67 ASR A
(0091) ; Load bank 0 table:
(0092) mov A, >LoadConfigTBL_freq_occur_ad_to_pwm_Bank0
02BE: 50 01 MOV A,1
(0093) mov X, <LoadConfigTBL_freq_occur_ad_to_pwm_Bank0
02C0: 57 FF MOV X,255
(0094) lcall LoadConfig ; Load the bank 0 values
02C2: 7C 02 D1 LCALL 0x02D1
(0095)
(0096) mov a, 1 ; Specify bank 1
02C5: 50 01 MOV A,1
(0097) asr a ; Store in carry flag
02C7: 67 ASR A
(0098) ; Load bank 1 table:
(0099) mov A, >LoadConfigTBL_freq_occur_ad_to_pwm_Bank1
02C8: 50 02 MOV A,2
(0100) mov X, <LoadConfigTBL_freq_occur_ad_to_pwm_Bank1
02CA: 57 64 MOV X,100
(0101) lcall LoadConfig ; Load the bank 1 values
02CC: 7C 02 D1 LCALL 0x02D1
(0102)
(0103) pop x
02CF: 20 POP X
(0104)
(0105) RAM_EPILOGUE RAM_USE_CLASS_4
(0106) ret
02D0: 7F RET
(0107)
(0108)
(0109)
(0110)
(0111) ;---------------------------------------------------------------------------
(0112) ; LoadConfig - Set IO registers as specified in ROM table of (address,value)
(0113) ; pairs. Terminate on address=0xFF.
(0114) ;
(0115) ; INPUTS: [A,X] points to the table to be loaded
(0116) ; Flag Register Carry bit encodes the Register Bank
(0117) ; (Carry=0 => Bank 0; Carry=1 => Bank 1)
(0118) ;
(0119) ; RETURNS: nothing.
(0120) ;
(0121) ; STACK FRAME: X-4 I/O Bank 0/1 indicator
(0122) ; X-3 Temporary store for register address
(0123) ; X-2 LSB of config table address
(0124) ; X-1 MSB of config table address
(0125) ;
(0126) LoadConfig:
(0127) RAM_PROLOGUE RAM_USE_CLASS_2
(0128) add SP, 2 ; Set up local vars
02D1: 38 02 ADD SP,2
(0129) push X ; Save config table address on stack
02D3: 10 PUSH X
(0130) push A
02D4: 08 PUSH A
(0131) mov X, SP
02D5: 4F MOV X,SP
(0132) mov [X-4], 0 ; Set default Destination to Bank 0
02D6: 56 FC 00 MOV [X-4],0
(0133) jnc .BankSelectSaved ; Carry says Bank 0 is OK
02D9: D0 04 JNC 0x02DE
(0134) mov [X-4], 1 ; No Carry: default to Bank 1
02DB: 56 FC 01 MOV [X-4],1
(0135) .BankSelectSaved:
(0136) pop A
02DE: 18 POP A
(0137) pop X
02DF: 20 POP X
(0138)
(0139) LoadConfigLp:
(0140) M8C_SetBank0 ; Switch to bank 0
02E0: 70 EF AND F,239
(0141) M8C_ClearWDT ; Clear the watchdog for long inits
02E2: 62 E3 00 MOV REG[227],0
(0142) push X ; Preserve the config table address
02E5: 10 PUSH X
(0143) push A
02E6: 08 PUSH A
(0144) romx ; Load register address from table
02E7: 28 ROMX
(0145) cmp A, END_CONFIG_TABLE ; End of table?
02E8: 39 FF CMP A,255
(0146) jz EndLoadConfig ; Yes, go wrap it up
02EA: A0 1F JZ 0x030A
(0147) mov X, SP ;
02EC: 4F MOV X,SP
(0148) tst [X-4], 1 ; Loading IO Bank 1?
02ED: 48 FC 01 TST [X-4],1
(0149) jz .IOBankNowSet ; No, Bank 0 is fine
02F0: A0 03 JZ 0x02F4
(0150) M8C_SetBank1 ; Yes, switch to Bank 1
02F2: 71 10 OR F,16
(0151) .IOBankNowSet:
(0152) mov [X-3], A ; Stash the register address
02F4: 54 FD MOV [X-3],A
(0153) pop A ; Retrieve the table address
02F6: 18 POP A
(0154) pop X
02F7: 20 POP X
(0155) inc X ; Advance to the data byte
02F8: 75 INC X
(0156) adc A, 0
02F9: 09 00 ADC A,0
(0157) push X ; Save the config table address again
02FB: 10 PUSH X
(0158) push A
02FC: 08 PUSH A
(0159) romx ; load config data from the table
02FD: 28 ROMX
(0160) mov X, SP ; retrieve the register address
02FE: 4F MOV X,SP
(0161) mov X, [X-3]
02FF: 59 FD MOV X,[X-3]
(0162) mov reg[X], A ; Configure the register
0301: 61 00 MOV REG[X+0],A
(0163) pop A ; retrieve the table address
0303: 18 POP A
(0164) pop X
0304: 20 POP X
(0165) inc X ; advance to next table entry
0305: 75 INC X
(0166) adc A, 0
0306: 09 00 ADC A,0
(0167) jmp LoadConfigLp ; loop to configure another register
0308: 8F D7 JMP 0x02E0
(0168) EndLoadConfig:
(0169) add SP, -4
030A: 38 FC ADD SP,252
(0170) RAM_EPILOGUE RAM_USE_CLASS_2
(0171) ret
030C: 7F RET
FILE: lib\timer8.asm
(0001) ;;*****************************************************************************
(0002) ;;*****************************************************************************
(0003) ;; FILENAME: Timer8.asm
(0004) ;; Version: 2.4, Updated on 2005/10/05 at 10:27:18
(0005) ;; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004
(0006) ;;
(0007) ;; DESCRIPTION: Timer8 User Module software implementation file
(0008) ;; for the 22/24/27/29xxx PSoC family of devices
(0009) ;;
(0010) ;; NOTE: User Module APIs conform to the fastcall16 convention for marshalling
(0011) ;; arguments and observe the associated "Registers are volatile" policy.
(0012) ;; This means it is the caller's responsibility to preserve any values
(0013) ;; in the X and A registers that are still needed after the API functions
(0014) ;; returns. For Large Memory Model devices it is also the caller's
(0015) ;; responsibility to perserve any value in the CUR_PP, IDX_PP, MVR_PP and
(0016) ;; MVW_PP registers. Even though some of these registers may not be modified
(0017) ;; now, there is no guarantee that will remain the case in future releases.
(0018) ;;-----------------------------------------------------------------------------
(0019) ;; Copyright (c) Cypress MicroSystems 2000-2004. All Rights Reserved.
(0020) ;;*****************************************************************************
(0021) ;;*****************************************************************************
(0022)
(0023) include "m8c.inc"
(0024) include "memory.inc"
(0025) include "Timer8.inc"
(0026)
(0027) ;-----------------------------------------------
(0028) ; Global Symbols
(0029) ;-----------------------------------------------
(0030) export Timer8_EnableInt
(0031) export _Timer8_EnableInt
(0032) export Timer8_DisableInt
(0033) export _Timer8_DisableInt
(0034) export Timer8_Start
(0035) export _Timer8_Start
(0036) export Timer8_Stop
(0037) export _Timer8_Stop
(0038) export Timer8_WritePeriod
(0039) export _Timer8_WritePeriod
(0040) export Timer8_WriteCompareValue
(0041) export _Timer8_WriteCompareValue
(0042) export Timer8_bReadCompareValue
(0043) export _Timer8_bReadCompareValue
(0044) export Timer8_bReadTimer
(0045) export _Timer8_bReadTimer
(0046) export Timer8_bReadTimerSaveCV
(0047) export _Timer8_bReadTimerSaveCV
(0048)
(0049) ; The following functions are deprecated and subject to omission in future releases
(0050) ;
(0051) export bTimer8_ReadCompareValue ; deprecated
(0052) export _bTimer8_ReadCompareValue ; deprecated
(0053) export bTimer8_ReadTimer ; deprecated
(0054) export _bTimer8_ReadTimer ; deprecated
(0055) export bTimer8_ReadTimerSaveCV ; deprecated
(0056) export _bTimer8_ReadTimerSaveCV ; deprecated
(0057)
(0058) export bTimer8_ReadCounter ; obsolete
(0059) export _bTimer8_ReadCounter ; obsolete
(0060) export bTimer8_CaptureCounter ; obsolete
(0061) export _bTimer8_CaptureCounter ; obsolete
(0062)
(0063)
(0064) AREA freq_occur_ad_to_pwm_RAM (RAM,REL)
(0065)
(0066) ;-----------------------------------------------
(0067) ; Constant Definitions
(0068) ;-----------------------------------------------
(0069)
(0070)
(0071) ;-----------------------------------------------
(0072) ; Variable Allocation
(0073) ;-----------------------------------------------
(0074)
(0075)
(0076) AREA UserModules (ROM, REL)
(0077)
(0078) .SECTION
(0079) ;-----------------------------------------------------------------------------
(0080) ; FUNCTION NAME: Timer8_EnableInt
(0081) ;
(0082) ; DESCRIPTION:
(0083) ; Enables this timer's interrupt by setting the interrupt enable mask bit
(0084) ; associated with this User Module. This function has no effect until and
(0085) ; unless the global interrupts are enabled (for example by using the
(0086) ; macro M8C_EnableGInt).
(0087) ;-----------------------------------------------------------------------------
(0088) ;
(0089) ; ARGUMENTS: None.
(0090) ; RETURNS: Nothing.
(0091) ; SIDE EFFECTS:
(0092) ; The A and X registers may be modified by this or future implementations
(0093) ; of this function. The same is true for all RAM page pointer registers in
(0094) ; the Large Memory Model. When necessary, it is the calling function's
(0095) ; responsibility to perserve their values across calls to fastcall16
(0096) ; functions.
(0097) ;
(0098) Timer8_EnableInt:
(0099) _Timer8_EnableInt:
(0100) RAM_PROLOGUE RAM_USE_CLASS_1
(0101) Timer8_EnableInt_M
030D: 43 E1 01 OR REG[225],1
(0102) RAM_EPILOGUE RAM_USE_CLASS_1
(0103) ret
0310: 7F RET
(0104)
(0105) .ENDSECTION
(0106)
(0107)
(0108) .SECTION
(0109) ;-----------------------------------------------------------------------------
(0110) ; FUNCTION NAME: Timer8_DisableInt
(0111) ;
(0112) ; DESCRIPTION:
(0113) ; Disables this timer's interrupt by clearing the interrupt enable
(0114) ; mask bit associated with this User Module.
(0115) ;-----------------------------------------------------------------------------
(0116) ;
(0117) ; ARGUMENTS: None
(0118) ; RETURNS: Nothing
(0119) ; SIDE EFFECTS:
(0120) ; The A and X registers may be modified by this or future implementations
(0121) ; of this function. The same is true for all RAM page pointer registers in
(0122) ; the Large Memory Model. When necessary, it is the calling function's
(0123) ; responsibility to perserve their values across calls to fastcall16
(0124) ; functions.
(0125) ;
(0126) Timer8_DisableInt:
(0127) _Timer8_DisableInt:
(0128) RAM_PROLOGUE RAM_USE_CLASS_1
(0129) Timer8_DisableInt_M
0311: 41 E1 FE AND REG[225],254
(0130) RAM_EPILOGUE RAM_USE_CLASS_1
(0131) ret
0314: 7F RET
(0132)
(0133) .ENDSECTION
(0134)
(0135)
(0136) .SECTION
(0137) ;-----------------------------------------------------------------------------
(0138) ; FUNCTION NAME: Timer8_Start
(0139) ;
(0140) ; DESCRIPTION:
(0141) ; Sets the start bit in the Control register of this user module. The
(0142) ; timer will begin counting on the next input clock.
(0143) ;-----------------------------------------------------------------------------
(0144) ;
(0145) ; ARGUMENTS: None
(0146) ; RETURNS: Nothing
(0147) ; SIDE EFFECTS:
(0148) ; The A and X registers may be modified by this or future implementations
(0149) ; of this function. The same is true for all RAM page pointer registers in
(0150) ; the Large Memory Model. When necessary, it is the calling function's
(0151) ; responsibility to perserve their values across calls to fastcall16
(0152) ; functions.
(0153) ;
(0154) Timer8_Start:
(0155) _Timer8_Start:
(0156) RAM_PROLOGUE RAM_USE_CLASS_1
(0157) Timer8_Start_M
0315: 43 23 01 OR REG[35],1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -