m8c.inc

此程序是用CYPRESS单片机编写

ABF_CR0_ACOL2MUX:     equ 40h    ; MASK: Analog Column 2 Mux control
ABF_CR0_ABUF1EN:      equ 20h    ; MASK: Enable ACol 1 analog buffer (P0[5])
ABF_CR0_ABUF2EN:      equ 10h    ; MASK: Enable ACol 2 analog buffer (P0[4])
ABF_CR0_ABUF0EN:      equ 08h    ; MASK: Enable ACol 0 analog buffer (P0[3])
ABF_CR0_ABUF3EN:      equ 04h    ; MASK: Enable ACol 3 analog buffer (P0[2])
ABF_CR0_BYPASS:       equ 02h    ; MASK: Bypass the analog buffers
ABF_CR0_PWR:          equ 01h    ; MASK: High power mode on all analog buffers

AMD_CR0:      equ 63h          ; Analog Modulator Control Register 0      (RW)
AMD_CR0_AMOD2:        equ 70h    ; MASK: Modulation source for analog column 2
AMD_CR0_AMOD0:        equ 07h    ; MASK: Modulation source for analog column 1

AMD_CR1:      equ 66h          ; Analog Modulator Control Register 1      (RW)
AMD_CR1_AMOD3:        equ 70h    ; MASK: Modulation ctrl for analog column 3
AMD_CR1_AMOD1:        equ 07h    ; MASK: Modulation ctrl for analog column 1

ALT_CR0:      equ 67h          ; Analog Look Up Table (LUT) Register 0    (RW)
ALT_CR0_LUT1:         equ F0h    ; MASK: Look up table 1 selection
ALT_CR0_LUT0:         equ 0Fh    ; MASK: Look up table 0 selection

ALT_CR1:      equ 68h          ; Analog Look Up Table (LUT) Register 1    (RW)
ALT_CR1_LUT3:         equ F0h    ; MASK: Look up table 3 selection
ALT_CR1_LUT2:         equ 0Fh    ; MASK: Look up table 2 selection

CLK_CR2:      equ 69h          ; Analog Clock Source Control Register 2   (RW)
CLK_CR2_ACLK1R:       equ 08h    ; MASK: Analog Clock 1 selection range
CLK_CR2_ACLK0R:       equ 01h    ; MASK: Analog Clock 0 selection range

;------------------------------------------------
;  Global Digital Interconnects
;------------------------------------------------

GDI_O_IN:     equ D0h          ; Global Dig Interconnect Odd Inputs Reg   (RW)
GDI_E_IN:     equ D1h          ; Global Dig Interconnect Even Inputs Reg  (RW)
GDI_O_OU:     equ D2h          ; Global Dig Interconnect Odd Outputs Reg  (RW)
GDI_E_OU:     equ D3h          ; Global Dig Interconnect Even Outputs Reg (RW)

;------------------------------------------------
;  Clock and System Control Registers
;------------------------------------------------

OSC_GO_EN:    equ DDh          ; Oscillator to Global Outputs Enable Register (RW)
OSC_GOEN_SLPINT:      equ 80h	 ; Enable Sleep Timer onto GOE[7]
OSC_GOEN_VC3:         equ 40h    ; Enable VC3 onto GOE[6]
OSC_GOEN_VC2:         equ 20h    ; Enable VC2 onto GOE[5]
OSC_GOEN_VC1:         equ 10h    ; Enable VC1 onto GOE[4]
OSC_GOEN_SYSCLKX2:    equ 08h    ; Enable 2X SysClk onto GOE[3]
OSC_GOEN_SYSCLK:      equ 04h    ; Enable 1X SysClk onto GOE[2]
OSC_GOEN_CLK24M:      equ 02h    ; Enable 24 MHz clock onto GOE[1]
OSC_GOEN_CLK32K:      equ 01h    ; Enable 32 kHz clock onto GOE[0]

OSC_CR4:      equ DEh          ; Oscillator Control Register 4            (RW)
OSC_CR4_VC3:          equ 03h    ; MASK: System VC3 Clock source

OSC_CR3:      equ DFh          ; Oscillator Control Register 3            (RW)

OSC_CR0:      equ E0h          ; System Oscillator Control Register 0     (RW)
OSC_CR0_32K_SELECT:   equ 80h    ; MASK: Enable/Disable External XTAL Osc
OSC_CR0_PLL_MODE:     equ 40h    ; MASK: Enable/Disable PLL
OSC_CR0_NO_BUZZ:      equ 20h    ; MASK: Bandgap always powered/BUZZ bandgap
OSC_CR0_SLEEP:        equ 18h    ; MASK: Set Sleep timer freq/period
OSC_CR0_SLEEP_512Hz:  equ 00h    ;     Set sleep bits for 1.95ms period
OSC_CR0_SLEEP_64Hz:   equ 08h    ;     Set sleep bits for 15.6ms period
OSC_CR0_SLEEP_8Hz:    equ 10h    ;     Set sleep bits for 125ms period
OSC_CR0_SLEEP_1Hz:    equ 18h    ;     Set sleep bits for 1 sec period
OSC_CR0_CPU:          equ 07h    ; MASK: Set CPU Frequency
OSC_CR0_CPU_3MHz:     equ 00h    ;     set CPU Freq bits for 3MHz Operation
OSC_CR0_CPU_6MHz:     equ 01h    ;     set CPU Freq bits for 6MHz Operation
OSC_CR0_CPU_12MHz:    equ 02h    ;     set CPU Freq bits for 12MHz Operation
OSC_CR0_CPU_24MHz:    equ 03h    ;     set CPU Freq bits for 24MHz Operation
OSC_CR0_CPU_1d5MHz:   equ 04h    ;     set CPU Freq bits for 1.5MHz Operation
OSC_CR0_CPU_750kHz:   equ 05h    ;     set CPU Freq bits for 750kHz Operation
OSC_CR0_CPU_187d5kHz: equ 06h    ;     set CPU Freq bits for 187.5kHz Operation
OSC_CR0_CPU_93d7kHz:  equ 07h    ;     set CPU Freq bits for 93.7kHz Operation

OSC_CR1:      equ E1h          ; System VC1/VC2 Divider Control Register  (RW)
OSC_CR1_VC1:          equ F0h    ; MASK: System VC1 24MHz/External Clk divider
OSC_CR1_VC2:          equ 0Fh    ; MASK: System VC2 24MHz/External Clk divider

OSC_CR2:      equ E2h          ; Oscillator Control Register 2            (RW)
OSC_CR2_PLLGAIN:      equ 80h    ; MASK: High/Low gain
OSC_CR2_EXTCLKEN:     equ 04h    ; MASK: Enable/Disable External Clock
OSC_CR2_IMODIS:       equ 02h    ; MASK: Enable/Disable System (IMO) Clock Net
OSC_CR2_SYSCLKX2DIS:  equ 01h    ; MASK: Enable/Disable 48MHz clock source

VLT_CR:       equ E3h          ; Voltage Monitor Control Register         (RW)
VLT_CR_SMP:           equ 80h    ; MASK: Enable Switch Mode Pump
VLT_CR_PORLEV:        equ 30h    ; MASK: Mask for Power on Reset level control
VLT_CR_POR_LOW:       equ 00h    ;   Lowest  Precision Power-on Reset trip point
VLT_CR_POR_MID:       equ 10h    ;   Middle  Precision Power-on Reset trip point
VLT_CR_POR_HIGH:      equ 20h    ;   Highest Precision Power-on Reset trip point
VLT_CR_LVDTBEN:       equ 08h    ; MASK: Enable the CPU Throttle Back on LVD
VLT_CR_VM:            equ 07h    ; MASK: Mask for Voltage Monitor level setting
VLT_CR_3V0_POR:       equ 00h    ; -- deprecated symbols --
VLT_CR_4V5_POR:       equ 10h    ;    deprecated
VLT_CR_4V75_POR:      equ 20h    ;    deprecated
VLT_CR_DISABLE:       equ 30h    ;    deprecated

VLT_CMP:      equ E4h          ; Voltage Monitor Comparators Register     (R)
VLT_CMP_PUMP:         equ 08h    ; MASK: Vcc below SMP trip level
VLT_CMP_LVD:          equ 08h    ; MASK: Vcc below LVD trip level
VLT_CMP_PPOR:         equ 08h    ; MASK: Vcc below PPOR trip level

IMO_TR:       equ E8h          ; Internal Main Oscillator Trim Register   (W)
ILO_TR:       equ E9h          ; Internal Low-speed Oscillator Trim       (W)
BDG_TR:       equ EAh          ; Band Gap Trim Register                   (W)
ECO_TR:       equ EBh          ; External Oscillator Trim Register        (W)

;;=============================================================================
;;      M8C System Macros
;;  These macros should be used when their functions are needed.
;;=============================================================================

;----------------------------------------------------
;  Swapping Register Banks
;----------------------------------------------------
    macro M8C_SetBank0
    and   F, ~FLAG_XIO_MASK
    endm

    macro M8C_SetBank1
    or    F, FLAG_XIO_MASK
    endm

;----------------------------------------------------
;  Global Interrupt Enable/Disable
;----------------------------------------------------
    macro M8C_EnableGInt
    or    F, FLAG_GLOBAL_IE
    endm

    macro M8C_DisableGInt
    and   F, ~FLAG_GLOBAL_IE
    endm

;----------------------------------------------------
;  Enable/Disable Interrupt Mask
;
;  Use the following macros to enable/disable
;  bits in the Interrupt mask registers,
;  INT_MSK0, INT_MSK1 or INT_MSK3.
;
;  Usage:    M8C_DisableIntMask INT_MSKN, MASK
;            M8C_EnableIntMask  INT_MSKN, MASK
;
;  where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
;        and MASK is the bit set to enable or disable
;----------------------------------------------------
; Disable Interrupt Bit Mask(s)
    macro M8C_DisableIntMask
    and   reg[@0], ~@1              ; disable specified interrupt enable bit
    endm

; Enable Interrupt Bit Mask(s)
    macro M8C_EnableIntMask
    or    reg[@0], @1               ; enable specified interrupt enable bit
    endm

;----------------------------------------------------
;  Clear Posted Interrupt Flag Mask
;
;  Use the following macros to clear the
;  bits in the Interrupt Clear registers,
;  INT_CLR0, INT_CLR1 or INT_CLR3.
;  Usage:    M8C_ClearIntFlag INT_CLRN, MASK
;
;  where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
;        and MASK is the bit set to enable or disable
;----------------------------------------------------
    macro M8C_ClearIntFlag
    mov   reg[@0], ~@1              ; clear specified interrupt enable bit
    endm

;----------------------------------------------------
;  Power-On Reset & WatchDog Timer Functions
;----------------------------------------------------
    macro M8C_EnableWatchDog
    and   reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
    endm

    macro M8C_ClearWDT
    mov   reg[RES_WDT], 00h
    endm

    macro M8C_ClearWDTAndSleep
    mov   reg[RES_WDT], 38h
    endm

;----------------------------------------------------
;  CPU Stall for Analog PSoC Block Writes
;----------------------------------------------------
    macro M8C_Stall
    or    reg[ASY_CR], ASY_CR_SYNCEN
    endm

    macro M8C_Unstall
    and   reg[ASY_CR], ~ASY_CR_SYNCEN
    endm

;----------------------------------------------------
;  Sleep, CPU Stop & Software Reset
;----------------------------------------------------
    macro M8C_Sleep
    or    reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
    ; The next instruction to be executed depends on the state of the
    ; various interrupt enable bits. If some interrupts are enabled
    ; and the global interrupts are disabled, the next instruction will
    ; be the one that follows the invocation of this macro. If global
    ; interrupts are also enabled then the next instruction will be
    ; from the interrupt vector table. If no interrupts are enabled
    ; then the CPU sleeps forever.
    endm

    macro M8C_Stop
    ; In general, you probably don't want to do this, but here's how:
    or    reg[CPU_SCR0], CPU_SCR0_STOP_MASK
    ; Next instruction to be executed is located in the interrupt
    ; vector table entry for Power-On Reset.
    endm

    macro M8C_Reset
    ; Restore CPU to the power-on reset state.
    mov A, 0
    SSC
    ; Next non-supervisor instruction will be at interrupt vector 0.
    endm

;----------------------------------------------------
; ImageCraft Code Compressor Actions
;----------------------------------------------------
    ; Suspend Code Compressor
    ; Must not span a RET or RETI instruction
    ; without resuming code compression
    macro Suspend_CodeCompressor
    or   F, 0
    endm

    ; Resume Code Compression
    macro Resume_CodeCompressor
    add  SP, 0
    endm

; end of file m8c.inc