📄 m8c.inc
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;------------------------------------------------
; Row Digital Interconnects
;
; Note: the following registers are mapped into
; both register bank 0 AND register bank 1.
;------------------------------------------------
RDI0RI: equ B0h ; Row Digital Interconnect Row 0 Input Reg (RW)
RDI0SYN: equ B1h ; Row Digital Interconnect Row 0 Sync Reg (RW)
RDI0IS: equ B2h ; Row 0 Input Select Register (RW)
RDI0LT0: equ B3h ; Row 0 Look Up Table Register 0 (RW)
RDI0LT1: equ B4h ; Row 0 Look Up Table Register 1 (RW)
RDI0RO0: equ B5h ; Row 0 Output Register 0 (RW)
RDI0RO1: equ B6h ; Row 0 Output Register 1 (RW)
RDI1RI: equ B8h ; Row Digital Interconnect Row 1 Input Reg (RW)
RDI1SYN: equ B9h ; Row Digital Interconnect Row 1 Sync Reg (RW)
RDI1IS: equ BAh ; Row 1 Input Select Register (RW)
RDI1LT0: equ BBh ; Row 1 Look Up Table Register 0 (RW)
RDI1LT1: equ BCh ; Row 1 Look Up Table Register 1 (RW)
RDI1RO0: equ BDh ; Row 1 Output Register 0 (RW)
RDI1RO1: equ BEh ; Row 1 Output Register 1 (RW)
;------------------------------------------------
; I2C Configuration Registers
;------------------------------------------------
I2C_CFG: equ D6h ; I2C Configuration Register (RW)
I2C_CFG_PINSEL: equ 40h ; MASK: Select P1[0] and P1[1] for I2C
I2C_CFG_BUSERR_IE: equ 20h ; MASK: Enable interrupt on Bus Error
I2C_CFG_STOP_IE: equ 10h ; MASK: Enable interrupt on Stop
I2C_CFG_CLK_RATE_100K: equ 00h ; MASK: I2C clock set at 100K
I2C_CFG_CLK_RATE_400K: equ 04h ; MASK: I2C clock set at 400K
I2C_CFG_CLK_RATE_50K: equ 08h ; MASK: I2C clock set at 50K
I2C_CFG_CLK_RATE_1M6: equ 0Ch ; MASK: I2C clock set at 1.6M
I2C_CFG_CLK_RATE: equ 0Ch ; MASK: I2C clock rate setting mask
I2C_CFG_PSELECT_MASTER: equ 02h ; MASK: Enable I2C Master
I2C_CFG_PSELECT_SLAVE: equ 01h ; MASK: Enable I2C Slave
I2C_SCR: equ D7h ; I2C Status and Control Register (#)
I2C_SCR_BUSERR: equ 80h ; MASK: I2C Bus Error detected (RC)
I2C_SCR_LOSTARB: equ 40h ; MASK: I2C Arbitration lost (RC)
I2C_SCR_STOP: equ 20h ; MASK: I2C Stop detected (RC)
I2C_SCR_ACK: equ 10h ; MASK: ACK the last byte (RW)
I2C_SCR_ADDR: equ 08h ; MASK: Address rcv'd is Slave address (RC)
I2C_SCR_XMIT: equ 04h ; MASK: Set transfer to tranmit mode (RW)
I2C_SCR_LRB: equ 02h ; MASK: Last recieved bit (RC)
I2C_SCR_BYTECOMPLETE: equ 01h ; MASK: Transfer of byte complete (RC)
I2C_DR: equ D8h ; I2C Data Register (RW)
I2C_MSCR: equ D9h ; I2C Master Status and Control Register (#)
I2C_MSCR_BUSY: equ 08h ; MASK: I2C Busy (Start detected) (R)
I2C_MSCR_MODE: equ 04h ; MASK: Start has been generated (R)
I2C_MSCR_RESTART: equ 02h ; MASK: Generate a Restart condition (RW)
I2C_MSCR_START: equ 01h ; MASK: Generate a Start condition (RW)
;------------------------------------------------
; System and Global Resource Registers
;------------------------------------------------
INT_CLR0: equ DAh ; Interrupt Clear Register 0 (RW)
; Use INT_MSK0 bit field masks
INT_CLR1: equ DBh ; Interrupt Clear Register 1 (RW)
; Use INT_MSK1 bit field masks
INT_CLR3: equ DDh ; Interrupt Clear Register 3 (RW)
; Use INT_MSK3 bit field masks
INT_MSK3: equ DEh ; I2C and Software Mask Register (RW)
INT_MSK3_ENSWINT: equ 80h ; MASK: enable/disable SW interrupt
INT_MSK3_I2C: equ 01h ; MASK: enable/disable I2C interrupt
INT_MSK0: equ E0h ; General Interrupt Mask Register (RW)
INT_MSK0_VC3: equ 80h ; MASK: enable/disable VC3 interrupt
INT_MSK0_SLEEP: equ 40h ; MASK: enable/disable sleep interrupt
INT_MSK0_GPIO: equ 20h ; MASK: enable/disable GPIO interrupt
INT_MSK0_ACOLUMN_3: equ 10h ; MASK: enable/disable Analog col 3 interrupt
INT_MSK0_ACOLUMN_2: equ 08h ; MASK: enable/disable Analog col 2 interrupt
INT_MSK0_ACOLUMN_1: equ 04h ; MASK: enable/disable Analog col 1 interrupt
INT_MSK0_ACOLUMN_0: equ 02h ; MASK: enable/disable Analog col 0 interrupt
INT_MSK0_VOLTAGE_MONITOR: equ 01h ; MASK: enable/disable Volts interrupt
INT_MSK1: equ E1h ; Digital PSoC block Mask Register (RW)
INT_MSK1_DCB13: equ 80h ; MASK: enable/disable DCB13 block interrupt
INT_MSK1_DCB12: equ 40h ; MASK: enable/disable DCB12 block interrupt
INT_MSK1_DBB11: equ 20h ; MASK: enable/disable DBB11 block interrupt
INT_MSK1_DBB10: equ 10h ; MASK: enable/disable DBB10 block interrupt
INT_MSK1_DCB03: equ 08h ; MASK: enable/disable DCB03 block interrupt
INT_MSK1_DCB02: equ 04h ; MASK: enable/disable DCB02 block interrupt
INT_MSK1_DBB01: equ 02h ; MASK: enable/disable DBB01 block interrupt
INT_MSK1_DBB00: equ 01h ; MASK: enable/disable DBB00 block interrupt
INT_VC: equ E2h ; Interrupt vector register (RC)
RES_WDT: equ E3h ; Watch Dog Timer Register (W)
; DECIMATOR Registers
DEC_DH: equ E4h ; Data Register (high byte) (RC)
DEC_DL: equ E5h ; Data Register ( low byte) (RC)
DEC_CR0: equ E6h ; Data Control Register 0 (RW)
DEC_CR1: equ E7h ; Data Control Register 1 (RW)
; Multiplier and MAC (Multiply/Accumulate) Unit
MUL_X: equ E8h ; Multiplier X Register (write) (W)
MUL_Y: equ E9h ; Multiplier Y Register (write) (W)
MUL_DH: equ EAh ; Multiplier Result Data (high byte read) (R)
MUL_DL: equ EBh ; Multiplier Result Data ( low byte read) (R)
MAC_X: equ ECh ; write = MAC X register [also see ACC_DR1]
ACC_DR1: equ MAC_X ; read = MAC Accumulator, byte 1 (RW)
MAC_Y: equ EDh ; write = MAC Y register [also see ACC_DR0]
ACC_DR0: equ MAC_Y ; read = MAC Accumulator, byte 0 (RW)
MAC_CL0: equ EEh ; write = MAC Clear Accum [also see ACC_DR3]
ACC_DR3: equ MAC_CL0 ; read = MAC Accumulator, byte 3 (RW)
MAC_CL1: equ EFh ; write = MAC Clear Accum [also see ACC_DR2]
ACC_DR2: equ MAC_CL1 ; read = MAC Accumulator, byte 2 (RW)
;------------------------------------------------------
; System Status and Control Registers
;
; Note: The following registers are mapped into both
; register bank 0 AND register bank 1.
;------------------------------------------------------
CPU_F: equ F7h ; CPU Flag Register Access (RO)
; Use FLAG_ masks defined at top of file
CPU_SCR1: equ FEh ; CPU Status and Control Register #1 (#)
CPU_SCR1_SLIMO: equ 10h ; MASK: Slow IMO (internal main osc) enable
CPU_SCR1_IRESS: equ 80h ; MASK: flag, Internal Reset Status bit
CPU_SCR1_ECO_ALWD_WR: equ 08h ; MASK: flag, ECO allowed has been written
CPU_SCR1_ECO_ALLOWED: equ 04h ; MASK: ECO allowed to be enabled
CPU_SCR1_IRAMDIS: equ 01h ; MASK: Disable RAM initialization on WDR
CPU_SCR0: equ FFh ; CPU Status and Control Register #2 (#)
CPU_SCR0_GIE_MASK: equ 80h ; MASK: Global Interrupt Enable shadow
CPU_SCR0_WDRS_MASK: equ 20h ; MASK: Watch Dog Timer Reset
CPU_SCR0_PORS_MASK: equ 10h ; MASK: power-on reset bit PORS
CPU_SCR0_SLEEP_MASK: equ 08h ; MASK: Enable Sleep
CPU_SCR0_STOP_MASK: equ 01h ; MASK: Halt CPU bit
;;=============================================================================
;; Register Space, Bank 1
;;=============================================================================
;------------------------------------------------
; Port Registers
; Note: Also see this address range in Bank 0.
;------------------------------------------------
; Port 0
PRT0DM0: equ 00h ; Port 0 Drive Mode 0 (RW)
PRT0DM1: equ 01h ; Port 0 Drive Mode 1 (RW)
PRT0IC0: equ 02h ; Port 0 Interrupt Control 0 (RW)
PRT0IC1: equ 03h ; Port 0 Interrupt Control 1 (RW)
; Port 1
PRT1DM0: equ 04h ; Port 1 Drive Mode 0 (RW)
PRT1DM1: equ 05h ; Port 1 Drive Mode 1 (RW)
PRT1IC0: equ 06h ; Port 1 Interrupt Control 0 (RW)
PRT1IC1: equ 07h ; Port 1 Interrupt Control 1 (RW)
; Port 2
PRT2DM0: equ 08h ; Port 2 Drive Mode 0 (RW)
PRT2DM1: equ 09h ; Port 2 Drive Mode 1 (RW)
PRT2IC0: equ 0Ah ; Port 2 Interrupt Control 0 (RW)
PRT2IC1: equ 0Bh ; Port 2 Interrupt Control 1 (RW)
; Port 3
PRT3DM0: equ 0Ch ; Port 3 Drive Mode 0 (RW)
PRT3DM1: equ 0Dh ; Port 3 Drive Mode 1 (RW)
PRT3IC0: equ 0Eh ; Port 3 Interrupt Control 0 (RW)
PRT3IC1: equ 0Fh ; Port 3 Interrupt Control 1 (RW)
; Port 4
PRT4DM0: equ 10h ; Port 4 Drive Mode 0 (RW)
PRT4DM1: equ 11h ; Port 4 Drive Mode 1 (RW)
PRT4IC0: equ 12h ; Port 4 Interrupt Control 0 (RW)
PRT4IC1: equ 13h ; Port 4 Interrupt Control 1 (RW)
; Port 5
PRT5DM0: equ 14h ; Port 5 Drive Mode 0 (RW)
PRT5DM1: equ 15h ; Port 5 Drive Mode 1 (RW)
PRT5IC0: equ 16h ; Port 5 Interrupt Control 0 (RW)
PRT5IC1: equ 17h ; Port 5 Interrupt Control 1 (RW)
;------------------------------------------------
; Digital PSoC(tm) block Registers
; Note: Also see this address range in Bank 0.
;------------------------------------------------
; Digital PSoC block 00, Basic Type B
DBB00FN: equ 20h ; Function Register (RW)
DBB00IN: equ 21h ; Input Register (RW)
DBB00OU: equ 22h ; Output Register (RW)
; Digital PSoC block 01, Basic Type B
DBB01FN: equ 24h ; Function Register (RW)
DBB01IN: equ 25h ; Input Register (RW)
DBB01OU: equ 26h ; Output Register (RW)
; Digital PSoC block 02, Communications Type B
DCB02FN: equ 28h ; Function Register (RW)
DCB02IN: equ 29h ; Input Register (RW)
DCB02OU: equ 2Ah ; Output Register (RW)
; Digital PSoC block 03, Communications Type B
DCB03FN: equ 2Ch ; Function Register (RW)
DCB03IN: equ 2Dh ; Input Register (RW)
DCB03OU: equ 2Eh ; Output Register (RW)
; Digital PSoC block 10, Basic Type B
DBB10FN: equ 30h ; Function Register (RW)
DBB10IN: equ 31h ; Input Register (RW)
DBB10OU: equ 32h ; Output Register (RW)
; Digital PSoC block 11, Basic Type B
DBB11FN: equ 34h ; Function Register (RW)
DBB11IN: equ 35h ; Input Register (RW)
DBB11OU: equ 36h ; Output Register (RW)
; Digital PSoC block 12, Communications Type B
DCB12FN: equ 38h ; Function Register (RW)
DCB12IN: equ 39h ; Input Register (RW)
DCB12OU: equ 3Ah ; Output Register (RW)
; Digital PSoC block 13, Communications Type B
DCB13FN: equ 3Ch ; Function Register (RW)
DCB13IN: equ 3Dh ; Input Register (RW)
DCB13OU: equ 3Eh ; Output Register (RW)
;------------------------------------------------
; System and Global Resource Registers
; Note: Also see this address range in Bank 0.
;------------------------------------------------
CLK_CR0: equ 60h ; Analog Column Clock Select Register 0 (RW)
CLK_CR0_ACOLUMN_3: equ C0h ; MASK: Specify clock for analog cloumn
CLK_CR0_ACOLUMN_2: equ 30h ; MASK: Specify clock for analog cloumn
CLK_CR0_ACOLUMN_1: equ 0Ch ; MASK: Specify clock for analog cloumn
CLK_CR0_ACOLUMN_0: equ 03h ; MASK: Specify clock for analog cloumn
CLK_CR1: equ 61h ; Analog Clock Source Select Register 1 (RW)
CLK_CR1_SHDIS: equ 40h ; MASK: Sample and Hold Disable (all Columns)
CLK_CR1_ACLK1: equ 38h ; MASK: Digital PSoC block for analog source
CLK_CR1_ACLK2: equ 07h ; MASK: Digital PSoC block for analog source
ABF_CR0: equ 62h ; Analog Output Buffer Control Register 0 (RW)
ABF_CR0_ACOL1MUX: equ 80h ; MASK: Analog Column 1 Mux control
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