📄 m8c.inc
字号:
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;; M8C.INC -- M8C27000 Microcontroller Family System Declarations
;;;
;;; Copyright (c) 2003-2004, Cypress MicroSystems, Inc. All rights reserved.
;;;
;;;
;;; This file provides address constants, bit field masks and a set of macro
;;; facilities for the Cypress MicroSystems 27xxx Microcontroller family.
;;;
;;; Last Modified: August 2, 2004
;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;=============================================================================
;; Definition of abbreviations used in the descriptions below
;; (RW) The register or bit supports reads and writes
;; (W) The register or bit is write-only
;; (R) The register or bit is read-only
;; (#) Access to the register is bit specific (see the family datasheet)
;; (RC) The register or bit can be read, but writing a 0 will clear it,
;; writing a 1 will have no effect.
;;=============================================================================
;;=============================================================================
;; System Registers
;;=============================================================================
;----------------------------
; Flag Register Bit Fields
;----------------------------
FLAG_XIO_MASK: equ 10h
FLAG_SUPER: equ 08h
FLAG_CARRY: equ 04h
FLAG_ZERO: equ 02h
FLAG_GLOBAL_IE: equ 01h
;;=============================================================================
;; Register Space, Bank 0
;;=============================================================================
;------------------------------------------------
; Port Registers
; Note: Also see this address range in Bank 1.
;------------------------------------------------
; Port 0
PRT0DR: equ 00h ; Port 0 Data Register (RW)
PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
; Port 1
PRT1DR: equ 04h ; Port 1 Data Register (RW)
PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
; Port 2
PRT2DR: equ 08h ; Port 2 Data Register (RW)
PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
; Port 3
PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
; Port 4
PRT4DR: equ 10h ; Port 4 Data Register (RW)
PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
; Port 5
PRT5DR: equ 14h ; Port 5 Data Register (RW)
PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
;------------------------------------------------
; Digital PSoC(tm) block Registers
; Note: Also see this address range in Bank 1.
;------------------------------------------------
; Digital PSoC block 00, Basic Type B
DBB00DR0: equ 20h ; data register 0 (#)
DBB00DR1: equ 21h ; data register 1 (W)
DBB00DR2: equ 22h ; data register 2 (RW)
DBB00CR0: equ 23h ; control & status register 0 (#)
; Digital PSoC block 01, Basic Type B
DBB01DR0: equ 24h ; data register 0 (#)
DBB01DR1: equ 25h ; data register 1 (W)
DBB01DR2: equ 26h ; data register 2 (RW)
DBB01CR0: equ 27h ; control & status register 0 (#)
; Digital PSoC block 02, Communications Type B
DCB02DR0: equ 28h ; data register 0 (#)
DCB02DR1: equ 29h ; data register 1 (W)
DCB02DR2: equ 2Ah ; data register 2 (RW)
DCB02CR0: equ 2Bh ; control & status register 0 (#)
; Digital PSoC block 03, Communications Type B
DCB03DR0: equ 2Ch ; data register 0 (#)
DCB03DR1: equ 2Dh ; data register 1 (W)
DCB03DR2: equ 2Eh ; data register 2 (RW)
DCB03CR0: equ 2Fh ; control & status register 0 (#)
; Digital PSoC block 10, Basic Type B
DBB10DR0: equ 30h ; data register 0 (#)
DBB10DR1: equ 31h ; data register 1 (W)
DBB10DR2: equ 32h ; data register 2 (RW)
DBB10CR0: equ 33h ; control & status register 0 (#)
; Digital PSoC block 11, Basic Type B
DBB11DR0: equ 34h ; data register 0 (#)
DBB11DR1: equ 35h ; data register 1 (W)
DBB11DR2: equ 36h ; data register 2 (RW)
DBB11CR0: equ 37h ; control & status register 0 (#)
; Digital PSoC block 12, Communications Type B
DCB12DR0: equ 38h ; data register 0 (#)
DCB12DR1: equ 39h ; data register 1 (W)
DCB12DR2: equ 3Ah ; data register 2 (RW)
DCB12CR0: equ 3Bh ; control & status register 0 (#)
; Digital PSoC block 13, Communications Type B
DCB13DR0: equ 3Ch ; data register 0 (#)
DCB13DR1: equ 3Dh ; data register 1 (W)
DCB13DR2: equ 3Eh ; data register 2 (RW)
DCB13CR0: equ 3Fh ; control & status register 0 (#)
;-------------------------------------
; Analog Resource Control Registers
;-------------------------------------
AMX_IN: equ 60h ; Analog Input Multiplexor Control (RW)
AMX_IN_ACI3: equ C0h ; MASK: column 3 input mux
AMX_IN_ACI2: equ 30h ; MASK: column 2 input mux
AMX_IN_ACI1: equ 0Ch ; MASK: column 1 input mux
AMX_IN_ACI0: equ 03h ; MASK: column 0 input mux
ARF_CR: equ 63h ; Analog Reference Control Register (RW)
ARF_CR_HBE: equ 40h ; MASK: Bias level control
ARF_CR_REF: equ 38h ; MASK: Analog Reference controls
ARF_CR_REFPWR: equ 07h ; MASK: Analog Reference power
ARF_CR_APWR: equ 04h ; MASK: use deprecated; see datasheet
ARF_CR_SCPWR: equ 03h ; MASK: Switched Cap block power
CMP_CR0: equ 64h ; Analog Comparator Bus 0 Register (#)
CMP_CR0_COMP3: equ 80h ; MASK: Column 3 comparator state (R)
CMP_CR0_COMP2: equ 40h ; MASK: Column 2 comparator state (R)
CMP_CR0_COMP1: equ 20h ; MASK: Column 1 comparator state (R)
CMP_CR0_COMP0: equ 10h ; MASK: Column 0 comparator state (R)
CMP_CR0_AINT3: equ 08h ; MASK: Column 3 interrupt source (RW)
CMP_CR0_AINT2: equ 04h ; MASK: Column 2 interrupt source (RW)
CMP_CR0_AINT1: equ 02h ; MASK: Column 1 interrupt source (RW)
CMP_CR0_AINT0: equ 01h ; MASK: Column 0 interrupt source (RW)
ASY_CR: equ 65h ; Analog Synchronizaton Control (#)
ASY_CR_SARCOUNT: equ 70h ; MASK: SAR support: resolution count (W)
ASY_CR_SARSIGN: equ 08h ; MASK: SAR support: sign (RW)
ASY_CR_SARCOL: equ 06h ; MASK: SAR support: column spec (RW)
ASY_CR_SYNCEN: equ 01h ; MASK: Stall bit (RW)
CMP_CR1: equ 66h ; Analog Comparator Bus 1 Register (RW)
CMP_CR1_ASYNCH3: equ 80h ; MASK: Column 3 comparator bus synch
CMP_CR1_ASYNCH2: equ 40h ; MASK: Column 2 comparator bus synch
CMP_CR1_ASYNCH1: equ 20h ; MASK: Column 1 comparator bus synch
CMP_CR1_ASYNCH0: equ 10h ; MASK: Column 0 comparator bus synch
;---------------------------------------------------
; Analog PSoC block Registers
;
; Note: the following registers are mapped into
; both register bank 0 AND register bank 1.
;---------------------------------------------------
; Continuous Time PSoC block Type B Row 0 Col 0
ACB00CR3: equ 70h ; Control register 3 (RW)
ACB00CR0: equ 71h ; Control register 0 (RW)
ACB00CR1: equ 72h ; Control register 1 (RW)
ACB00CR2: equ 73h ; Control register 2 (RW)
; Continuous Time PSoC block Type B Row 0 Col 1
ACB01CR3: equ 74h ; Control register 3 (RW)
ACB01CR0: equ 75h ; Control register 0 (RW)
ACB01CR1: equ 76h ; Control register 1 (RW)
ACB01CR2: equ 77h ; Control register 2 (RW)
; Continuous Time PSoC block Type B Row 0 Col 2
ACB02CR3: equ 78h ; Control register 3 (RW)
ACB02CR0: equ 79h ; Control register 0 (RW)
ACB02CR1: equ 7Ah ; Control register 1 (RW)
ACB02CR2: equ 7Bh ; Control register 2 (RW)
; Continuous Time PSoC block Type B Row 0 Col 3
ACB03CR3: equ 7Ch ; Control register 3 (RW)
ACB03CR0: equ 7Dh ; Control register 0 (RW)
ACB03CR1: equ 7Eh ; Control register 1 (RW)
ACB03CR2: equ 7Fh ; Control register 2 (RW)
; Switched Cap PSoC blockType C Row 1 Col 0
ASC10CR0: equ 80h ; Control register 0 (RW)
ASC10CR1: equ 81h ; Control register 1 (RW)
ASC10CR2: equ 82h ; Control register 2 (RW)
ASC10CR3: equ 83h ; Control register 3 (RW)
; Switched Cap PSoC blockType D Row 1 Col 1
ASD11CR0: equ 84h ; Control register 0 (RW)
ASD11CR1: equ 85h ; Control register 1 (RW)
ASD11CR2: equ 86h ; Control register 2 (RW)
ASD11CR3: equ 87h ; Control register 3 (RW)
; Switched Cap PSoC blockType C Row 1 Col 2
ASC12CR0: equ 88h ; Control register 0 (RW)
ASC12CR1: equ 89h ; Control register 1 (RW)
ASC12CR2: equ 8Ah ; Control register 2 (RW)
ASC12CR3: equ 8Bh ; Control register 3 (RW)
; Switched Cap PSoC blockType D Row 1 Col 3
ASD13CR0: equ 8Ch ; Control register 0 (RW)
ASD13CR1: equ 8Dh ; Control register 1 (RW)
ASD13CR2: equ 8Eh ; Control register 2 (RW)
ASD13CR3: equ 8Fh ; Control register 3 (RW)
; Switched Cap PSoC blockType D Row 2 Col 0
ASD20CR0: equ 90h ; Control register 0 (RW)
ASD20CR1: equ 91h ; Control register 1 (RW)
ASD20CR2: equ 92h ; Control register 2 (RW)
ASD20CR3: equ 93h ; Control register 3 (RW)
; Switched Cap PSoC blockType C Row 2 Col 1
ASC21CR0: equ 94h ; Control register 0 (RW)
ASC21CR1: equ 95h ; Control register 1 (RW)
ASC21CR2: equ 96h ; Control register 2 (RW)
ASC21CR3: equ 97h ; Control register 3 (RW)
; Switched Cap PSoC blockType D Row 2 Col 2
ASD22CR0: equ 98h ; Control register 0 (RW)
ASD22CR1: equ 99h ; Control register 1 (RW)
ASD22CR2: equ 9Ah ; Control register 2 (RW)
ASD22CR3: equ 9Bh ; Control register 3 (RW)
; Switched Cap PSoC blockType C Row 2 Col 3
ASC23CR0: equ 9Ch ; Control register 0 (RW)
ASC23CR1: equ 9Dh ; Control register 1 (RW)
ASC23CR2: equ 9Eh ; Control register 2 (RW)
ASC23CR3: equ 9Fh ; Control register 3 (RW)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -