📄 m8c.h
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// Digital PSoC(tm) block Registers
// Note: Also see this address range in Bank 1.
//-----------------------------------------------
// Digital PSoC block 00, Basic Type B
#pragma ioport DBB00FN: 0x120 // Function Register
BYTE DBB00FN;
#pragma ioport DBB00IN: 0x121 // Input Register
BYTE DBB00IN;
#pragma ioport DBB00OU: 0x122 // Output Register
BYTE DBB00OU;
// Digital PSoC block 01, Basic Type B
#pragma ioport DBB01FN: 0x124 // Function Register
BYTE DBB01FN;
#pragma ioport DBB01IN: 0x125 // Input Register
BYTE DBB01IN;
#pragma ioport DBB01OU: 0x126 // Output Register
BYTE DBB01OU;
// Digital PSoC block 02, Communications Type B
#pragma ioport DCB02FN: 0x128 // Function Register
BYTE DCB02FN;
#pragma ioport DCB02IN: 0x129 // Input Register
BYTE DCB02IN;
#pragma ioport DCB02OU: 0x12A // Output Register
BYTE DCB02OU;
// Digital PSoC block 03, Communications Type B
#pragma ioport DCB03FN: 0x12C // Function Register
BYTE DCB03FN;
#pragma ioport DCB03IN: 0x12D // Input Register
BYTE DCB03IN;
#pragma ioport DCB03OU: 0x12E // Output Register
BYTE DCB03OU;
// Digital PSoC block 10, Basic Type B
#pragma ioport DBB10FN: 0x130 // Function Register
BYTE DBB10FN;
#pragma ioport DBB10IN: 0x131 // Input Register
BYTE DBB10IN;
#pragma ioport DBB10OU: 0x132 // Output Register
BYTE DBB10OU;
// Digital PSoC block 11, Basic Type B
#pragma ioport DBB11FN: 0x134 // Function Register
BYTE DBB11FN;
#pragma ioport DBB11IN: 0x135 // Input Register
BYTE DBB11IN;
#pragma ioport DBB11OU: 0x136 // Output Register
BYTE DBB11OU;
// Digital PSoC block 12, Communications Type B
#pragma ioport DCB12FN: 0x138 // Function Register
BYTE DCB12FN;
#pragma ioport DCB12IN: 0x139 // Input Register
BYTE DCB12IN;
#pragma ioport DCB12OU: 0x13A // Output Register
BYTE DCB12OU;
// Digital PSoC block 13, Communications Type B
#pragma ioport DCB13FN: 0x13C // Function Register
BYTE DCB13FN;
#pragma ioport DCB13IN: 0x13D // Input Register
BYTE DCB13IN;
#pragma ioport DCB13OU: 0x13E // Output Register
BYTE DCB13OU;
//-----------------------------------------------
// System and Global Resource Registers
// Note: Also see this address range in Bank 0.
//-----------------------------------------------
#pragma ioport CLK_CR0: 0x160 // Analog Column Clock Select Register
BYTE CLK_CR0;
#define CLK_CR0_ACOLUMN_3 (0xC0)
#define CLK_CR0_ACOLUMN_2 (0x30)
#define CLK_CR0_ACOLUMN_1 (0x0C)
#define CLK_CR0_ACOLUMN_0 (0x03)
#pragma ioport CLK_CR1: 0x161 // Analog Clock Source Select Register
BYTE CLK_CR1;
#define CLK_CR1_SHDIS (0x40)
#define CLK_CR1_ACLK1 (0x38)
#define CLK_CR1_ACLK2 (0x07)
#pragma ioport ABF_CR0: 0x162 // Analog Output Buffer Control Register
BYTE ABF_CR0;
#define ABF_CR0_ACOL1MUX (0x80)
#define ABF_CR0_ACOL2MUX (0x40)
#define ABF_CR0_ABUF1EN (0x20)
#define ABF_CR0_ABUF2EN (0x10)
#define ABF_CR0_ABUF0EN (0x08)
#define ABF_CR0_ABUF3EN (0x04)
#define ABF_CR0_BYPASS (0x02)
#define ABF_CR0_PWR (0x01)
#pragma ioport AMD_CR0: 0x163 // Analog Modulator Control Register
BYTE AMD_CR0;
#define AMD_CR0_AMOD2 (0x70)
#define AMD_CR0_AMOD0 (0x07)
#pragma ioport AMD_CR1: 0x166 // Analog Modulator Control Register 1
BYTE AMD_CR1;
#define AMD_CR1_AMOD3 (0x70)
#define AMD_CR1_AMOD1 (0x07)
#pragma ioport ALT_CR0: 0x167 // Analog Look Up Table (LUT) Register 0
BYTE ALT_CR0;
#define ALT_CR0_LUT1 (0xF0)
#define ALT_CR0_LUT0 (0x0F)
#pragma ioport ALT_CR1: 0x168 // Analog Look Up Table (LUT) Register 1
BYTE ALT_CR1;
#define ALT_CR1_LUT3 (0xF0)
#define ALT_CR1_LUT2 (0x0F)
#pragma ioport CLK_CR2: 0x169 // Analog Clock Source Control Register 2
BYTE CLK_CR2;
#define CLK_CR2_ACLK1R (0x08)
#define CLK_CR2_ACLK0R (0x01)
//-----------------------------------------------
// Global Digital Interconnects
//-----------------------------------------------
#pragma ioport GDI_O_IN: 0x1D0 // Global Dig Interconnect Odd Inputs
BYTE GDI_O_IN;
#pragma ioport GDI_E_IN: 0x1D1 // Global Dig Interconnect Even Inputs
BYTE GDI_E_IN;
#pragma ioport GDI_O_OU: 0x1D2 // Global Dig Interconnect Odd Outputs
BYTE GDI_O_OU;
#pragma ioport GDI_E_OU: 0x1D3 // Global Dig Interconnect Even Outputs
BYTE GDI_E_OU;
//------------------------------------------------
// Clock and System Control Registers
//------------------------------------------------
#pragma ioport OSC_GO_EN: 0x1DD // Oscillator to Global Outputs Enable Register (RW)
BYTE OSC_GO_EN;
#define OSC_GOEN_SLPINT (0x80)
#define OSC_GOEN_VC3 (0x40)
#define OSC_GOEN_VC2 (0x20)
#define OSC_GOEN_VC1 (0x10)
#define OSC_GOEN_SYSCLKX2 (0x08)
#define OSC_GOEN_SYSCLK (0x04)
#define OSC_GOEN_CLK24M (0x02)
#define OSC_GOEN_CLK32K (0x01)
#pragma ioport OSC_CR4: 0x1DE // Oscillator Control Register 4
BYTE OSC_CR4;
// recommended:
#define OSC_CR4_VC3SEL (0x03)
// deprecated:
#define OSC_CR4_VC3 (0x03)
#pragma ioport OSC_CR3: 0x1DF // Oscillator Control Register 3
BYTE OSC_CR3;
#pragma ioport OSC_CR0: 0x1E0 // System Oscillator Control Register 0
BYTE OSC_CR0;
#define OSC_CR0_32K_SELECT (0x80)
#define OSC_CR0_PLL_MODE (0x40)
#define OSC_CR0_NO_BUZZ (0x20)
#define OSC_CR0_SLEEP (0x18)
#define OSC_CR0_SLEEP_512Hz (0x00)
#define OSC_CR0_SLEEP_64Hz (0x08)
#define OSC_CR0_SLEEP_8Hz (0x10)
#define OSC_CR0_SLEEP_1Hz (0x18)
#define OSC_CR0_CPU (0x07)
#define OSC_CR0_CPU_3MHz (0x00)
#define OSC_CR0_CPU_6MHz (0x01)
#define OSC_CR0_CPU_12MHz (0x02)
#define OSC_CR0_CPU_24MHz (0x03)
#define OSC_CR0_CPU_1d5MHz (0x04)
#define OSC_CR0_CPU_750kHz (0x05)
#define OSC_CR0_CPU_187d5kHz (0x06)
#define OSC_CR0_CPU_93d7kHz (0x07)
#pragma ioport OSC_CR1: 0x1E1 // System V1/V2 Divider Control Register
BYTE OSC_CR1;
#define OSC_CR1_VC1 (0xF0)
#define OSC_CR1_VC2 (0x0F)
#pragma ioport OSC_CR2: 0x1E2 // Oscillator Control Register 2
BYTE OSC_CR2;
#define OSC_CR2_PLLGAIN (0x80)
#define OSC_CR2_EXTCLKEN (0x04)
#define OSC_CR2_IMODIS (0x02)
#define OSC_CR2_SYSCLKX2DIS (0x01)
#pragma ioport VLT_CR: 0x1E3 // Voltage Monitor Control Register
BYTE VLT_CR;
#define VLT_CR_SMP (0x80)
#define VLT_CR_PORLEV (0x30)
#define VLT_CR_POR_LOW (0x00)
#define VLT_CR_POR_MID (0x10)
#define VLT_CR_POR_HIGH (0x20)
#define VLT_CR_LVDTBEN (0x08)
#define VLT_CR_VM (0x07)
// following names are deprecated
#define VLT_CR_3V0_POR (0x00)
#define VLT_CR_4V5_POR (0x10)
#define VLT_CR_4V75_POR (0x20)
#define VLT_CR_DISABLE (0x30)
#pragma ioport VLT_CMP: 0x1E4 // Voltage Monitor Comparators Register
BYTE VLT_CMP;
#define VLT_CMP_PUMP (0x08)
#define VLT_CMP_LVD (0x08)
#define VLT_CMP_PPOR (0x08)
#pragma ioport IMO_TR: 0x1E8 // Internal Main Oscillator Trim Register
BYTE IMO_TR;
#pragma ioport ILO_TR: 0x1E9 // Internal Low-speed Oscillator Trim
BYTE ILO_TR;
#pragma ioport BDG_TR: 0x1EA // Band Gap Trim Register
BYTE BDG_TR;
#pragma ioport ECO_TR: 0x1EB // External Oscillator Trim Register
BYTE ECO_TR;
//=============================================================================
//=============================================================================
// M8C System Macros
//=============================================================================
//=============================================================================
//-----------------------------------------------
// Swapping Register Banks
//-----------------------------------------------
#define M8C_SetBank0 asm("and F, EFh")
#define M8C_SetBank1 asm("or F, 10h")
//-----------------------------------------------
// Global Interrupt Enable/Disable
//-----------------------------------------------
#define M8C_EnableGInt asm("or F, 01h")
#define M8C_DisableGInt asm("and F, FEh")
//---------------------------------------------------
// Enable/Disable Interrupt Mask
//
// Usage: M8C_DisableIntMask INT_MSKN, MASK
// M8C_EnableIntMask INT_MSKN, MASK
//
// where INT_MSKN is INT_MSK0, INT_MSK1 or INT_MSK3
// and MASK is the bit set to enable or disable
//---------------------------------------------------
// Disable Interrupt Bit Mask(s)
#define M8C_DisableIntMask( INT_MSKN_REG, MASK ) (INT_MSKN_REG &= ~MASK)
// Enable Interrupt Bit Mask(s)
#define M8C_EnableIntMask( INT_MSKN_REG, MASK ) (INT_MSKN_REG |= MASK)
//---------------------------------------------------
// Clear Posted Interrupt Flag
//
// Usage: M8C_ClearIntFlag INT_CLRN, MASK
//
// where INT_MSKN is INT_CLR0, INT_CLR1 or INT_CLR3
// and MASK is the bit set to enable or disable
//---------------------------------------------------
#define M8C_ClearIntFlag( INT_CLRN_REG, MASK ) (INT_CLRN_REG = ~MASK)
//-----------------------------------------------
// Power-On Reset & WatchDog Timer Functions
//-----------------------------------------------
#define M8C_EnableWatchDog (CPU_SCR0 &= ~CPU_SCR0_PORS_MASK)
#define M8C_ClearWDT (RES_WDT = 0x00)
#define M8C_ClearWDTAndSleep (RES_WDT = 0x38)
//-----------------------------------------------
// CPU Stall for Analog PSoC Block Writes
//-----------------------------------------------
#define M8C_Stall (ASY_CR |= ASY_CR_SYNCEN)
#define M8C_Unstall (ASY_CR &= ~ASY_CR_SYNCEN)
//-----------------------------------------------
// Sleep, CPU Stop & Software Reset
//-----------------------------------------------
#define M8C_Sleep (CPU_SCR0 |= CPU_SCR0_SLEEP_MASK)
#define M8C_Stop (CPU_SCR0 |= CPU_SCR0_STOP_MASK)
#define M8C_Reset asm("mov A, 0\nSSC");
//-----------------------------------------------
// ImageCraft Code Compressor Actions
//-----------------------------------------------
// Suspend Code Compressor
// Must not span a RET or RETI instruction
// without resuming code compression
#define Suspend_CodeCompressor asm("or F, 0")
// Resume Code Compressor
#define Resume_CodeCompressor asm("add SP,0")
#endif
// end of file m8c.h
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