📄 m8c.h
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// Switched Cap PSoC Block Type C Row 1 Col 2
#pragma ioport ASC12CR0: 0x088 // Control register 0
BYTE ASC12CR0;
#pragma ioport ASC12CR1: 0x089 // Control register 1
BYTE ASC12CR1;
#pragma ioport ASC12CR2: 0x08A // Control register 2
BYTE ASC12CR2;
#pragma ioport ASC12CR3: 0x08B // Control register 3
BYTE ASC12CR3;
// Switched Cap PSoC Block Type D Row 1 Col 3
#pragma ioport ASD13CR0: 0x08C // Control register 0
BYTE ASD13CR0;
#pragma ioport ASD13CR1: 0x08D // Control register 1
BYTE ASD13CR1;
#pragma ioport ASD13CR2: 0x08E // Control register 2
BYTE ASD13CR2;
#pragma ioport ASD13CR3: 0x08F // Control register 3
BYTE ASD13CR3;
// Switched Cap PSoC Block Type D Row 2 Col 0
#pragma ioport ASD20CR0: 0x090 // Control register 0
BYTE ASD20CR0;
#pragma ioport ASD20CR1: 0x091 // Control register 1
BYTE ASD20CR1;
#pragma ioport ASD20CR2: 0x092 // Control register 2
BYTE ASD20CR2;
#pragma ioport ASD20CR3: 0x093 // Control register 3
BYTE ASD20CR3;
// Switched Cap PSoC Block Type C Row 2 Col 1
#pragma ioport ASC21CR0: 0x094 // Control register 0
BYTE ASC21CR0;
#pragma ioport ASC21CR1: 0x095 // Control register 1
BYTE ASC21CR1;
#pragma ioport ASC21CR2: 0x096 // Control register 2
BYTE ASC21CR2;
#pragma ioport ASC21CR3: 0x097 // Control register 3
BYTE ASC21CR3;
// Switched Cap PSoC Block Type D Row 2 Col 2
#pragma ioport ASD22CR0: 0x098 // Control register 0
BYTE ASD22CR0;
#pragma ioport ASD22CR1: 0x099 // Control register 1
BYTE ASD22CR1;
#pragma ioport ASD22CR2: 0x09A // Control register 2
BYTE ASD22CR2;
#pragma ioport ASD22CR3: 0x09B // Control register 3
BYTE ASD22CR3;
// Switched Cap PSoC Block Type C Row 2 Col 3
#pragma ioport ASC23CR0: 0x09C // Control register 0
BYTE ASC23CR0;
#pragma ioport ASC23CR1: 0x09D // Control register 1
BYTE ASC23CR1;
#pragma ioport ASC23CR2: 0x09E // Control register 2
BYTE ASC23CR2;
#pragma ioport ASC23CR3: 0x09F // Control register 3
BYTE ASC23CR3;
//-----------------------------------------------
// Row Digital Interconnects
//
// Note: the following registers are mapped into
// both register bank 0 AND register bank 1.
//-----------------------------------------------
#pragma ioport RDI0RI: 0x0B0 // Row Digital Interconnect Row 0 Input
BYTE RDI0RI;
#pragma ioport RDI0SYN: 0x0B1 // Row Digital Interconnect Row 0 Sync Reg
BYTE RDI0SYN;
#pragma ioport RDI0IS: 0x0B2 // Row 0 Input Select Register
BYTE RDI0IS;
#pragma ioport RDI0LT0: 0x0B3 // Row 0 Look Up Table Register 0
BYTE RDI0LT0;
#pragma ioport RDI0LT1: 0x0B4 // Row 0 Look Up Table Register 1
BYTE RDI0LT1;
#pragma ioport RDI0RO0: 0x0B5 // Row 0 Output Register 0
BYTE RDI0RO0;
#pragma ioport RDI0RO1: 0x0B6 // Row 0 Output Register 1
BYTE RDI0RO1;
#pragma ioport RDI1RI: 0x0B8 // Row Digital Interconnect Row 1 Input
BYTE RDI1RI;
#pragma ioport RDI1SYN: 0x0B9 // Row Digital Interconnect Row 1 Sync Reg
BYTE RDI1SYN;
#pragma ioport RDI1IS: 0x0BA // Row 1 Input Select Register
BYTE RDI1IS;
#pragma ioport RDI1LT0: 0x0BB // Row 1 Look Up Table Register 0
BYTE RDI1LT0;
#pragma ioport RDI1LT1: 0x0BC // Row 1 Look Up Table Register 1
BYTE RDI1LT1;
#pragma ioport RDI1RO0: 0x0BD // Row 1 Output Register 0
BYTE RDI1RO0;
#pragma ioport RDI1RO1: 0x0BE // Row 1 Output Register 1
BYTE RDI1RO1;
//-----------------------------------------------
// I2C Configuration Registers
//-----------------------------------------------
#pragma ioport I2C_CFG: 0x0D6 // I2C Configuration Register
BYTE I2C_CFG;
#define I2C_CFG_PINSEL (0x40)
#define I2C_CFG_BUSERR_IE (0x20)
#define I2C_CFG_STOP_IE (0x10)
#define I2C_CFG_CLK_RATE_100K (0x00)
#define I2C_CFG_CLK_RATE_400K (0x04)
#define I2C_CFG_CLK_RATE_50K (0x08)
#define I2C_CFG_CLK_RATE_1M6 (0x0C)
#define I2C_CFG_CLK_RATE (0x0C)
#define I2C_CFG_PSELECT_MASTER (0x02)
#define I2C_CFG_PSELECT_SLAVE (0x01)
#pragma ioport I2C_SCR: 0x0D7 // I2C Status and Control Register
BYTE I2C_SCR;
#define I2C_SCR_BUSERR (0x80)
#define I2C_SCR_LOSTARB (0x40)
#define I2C_SCR_STOP (0x20)
#define I2C_SCR_ACK (0x10)
#define I2C_SCR_ADDR (0x08)
#define I2C_SCR_XMIT (0x04)
#define I2C_SCR_LRB (0x02)
#define I2C_SCR_BYTECOMPLETE (0x01)
#pragma ioport I2C_DR: 0x0D8 // I2C Data Register
BYTE I2C_DR;
#pragma ioport I2C_MSCR: 0x0D9 // I2C Master Status and Control Register
BYTE I2C_MSCR;
#define I2C_MSCR_BUSY (0x08)
#define I2C_MSCR_MODE (0x04)
#define I2C_MSCR_RESTART (0x02)
#define I2C_MSCR_START (0x01)
//-----------------------------------------------
// System and Global Resource Registers
//-----------------------------------------------
#pragma ioport INT_CLR0: 0x0DA // Interrupt Clear Register 0
BYTE INT_CLR0;
#pragma ioport INT_CLR1: 0x0DB // Interrupt Clear Register 1
BYTE INT_CLR1;
#pragma ioport INT_CLR3: 0x0DD // Interrupt Clear Register 3
BYTE INT_CLR3;
#pragma ioport INT_MSK3: 0x0DE // I2C and Software Mask Register
BYTE INT_MSK3;
#define INT_MSK3_ENSWINT (0x80)
#define INT_MSK3_I2C (0x01)
#pragma ioport INT_MSK0: 0x0E0 // General Interrupt Mask Register
BYTE INT_MSK0;
#define INT_MSK0_VC3 (0x80)
#define INT_MSK0_SLEEP (0x40)
#define INT_MSK0_GPIO (0x20)
#define INT_MSK0_ACOLUMN_3 (0x10)
#define INT_MSK0_ACOLUMN_2 (0x08)
#define INT_MSK0_ACOLUMN_1 (0x04)
#define INT_MSK0_ACOLUMN_0 (0x02)
#define INT_MSK0_VOLTAGE_MONITOR (0x01)
#pragma ioport INT_MSK1: 0x0E1 // Digital PSoC block Mask Register
BYTE INT_MSK1;
#define INT_MSK1_DCB13 (0x80)
#define INT_MSK1_DCB12 (0x40)
#define INT_MSK1_DBB11 (0x20)
#define INT_MSK1_DBB10 (0x10)
#define INT_MSK1_DCB03 (0x08)
#define INT_MSK1_DCB02 (0x04)
#define INT_MSK1_DBB01 (0x02)
#define INT_MSK1_DBB00 (0x01)
#pragma ioport INT_VC: 0x0E2 // Interrupt vector register
BYTE INT_VC;
#pragma ioport RES_WDT: 0x0E3 // Watch Dog Timer
BYTE RES_WDT;
// DECIMATOR Registers
#pragma ioport DEC_DH: 0x0E4 // Data Register (high byte)
CHAR DEC_DH;
#pragma ioport DEC_DL: 0x0E5 // Data Register ( low byte)
CHAR DEC_DL;
#pragma ioport DEC_CR0: 0x0E6 // Data Control Register
BYTE DEC_CR0;
#pragma ioport DEC_CR1: 0x0E7 // Data Control Register
BYTE DEC_CR1;
// Multiplier and MAC (Multiply/Accumulate) Unit
#pragma ioport MUL_X: 0x0E8 // Multiplier X Register (write)
CHAR MUL_X;
#pragma ioport MUL_Y: 0x0E9 // Multiplier Y Register (write)
CHAR MUL_Y;
#pragma ioport MUL_DH: 0x0EA // Multiplier Result Data (high byte read)
CHAR MUL_DH;
#pragma ioport MUL_DL: 0x0EB // Multiplier Result Data ( low byte read)
CHAR MUL_DL;
#pragma ioport MUL_RESULT: 0x0EA // Multiplier Result Data - WORD
INT MUL_RESULT;
#pragma ioport MAC_X: 0x0EC // MAC X register (write) [see ACC_DR1]
CHAR MAC_X;
#pragma ioport MAC_Y: 0x0ED // MAC Y register (write) [see ACC_DR0]
CHAR MAC_Y;
#pragma ioport MAC_CL0: 0x0EE // MAC Clear Accum (write)[see ACC_DR3]
BYTE MAC_CL0;
#pragma ioport MAC_CL1: 0x0EF // MAC Clear Accum (write)[see ACC_DR2]
BYTE MAC_CL1;
#pragma ioport ACC_DR1: 0x0EC // MAC Accumulator (Read, byte 1)
CHAR ACC_DR1;
#pragma ioport ACC_DR0: 0x0ED // MAC Accumulator (Read, byte 0)
CHAR ACC_DR0;
#pragma ioport ACC_LOW_WORD: 0x0EC // MAC Accumulator (Read low word)
INT ACC_LOW_WORD;
#pragma ioport ACC_DR3: 0x0EE // MAC Accumulator (Read, byte 3)
CHAR ACC_DR3;
#pragma ioport ACC_DR2: 0x0EF // MAC Accumulator (Read, byte 2)
CHAR ACC_DR2;
#pragma ioport ACC_HI_WORD: 0x0EE // MAC Accumulator (Read high word)
INT ACC_HI_WORD;
//-----------------------------------------------
// System Status and Control Register
//
// Note: the following register is mapped into
// both register bank 0 AND register bank 1.
//-----------------------------------------------
#pragma ioport CPU_F: 0xF7 // CPU Flag Register Access
BYTE CPU_F; // Use FLAG_ masks defined at top of file
#pragma ioport CPU_SCR1: 0xFE // System Status and Control Register 1
BYTE CPU_SCR1;
#define CPU_SCR1_SLIMO (0x10)
#define CPU_SCR1_IRESS (0x80)
#define CPU_SCR1_ECO_ALWD_WR (0x08)
#define CPU_SCR1_ECO_ALLOWED (0x04)
#define CPU_SCR1_IRAMDIS (0x01)
#pragma ioport CPU_SCR0: 0x0FF // System Status and Control Register 0
BYTE CPU_SCR0;
#define CPU_SCR0_GIE_MASK (0x80)
#define CPU_SCR0_WDRS_MASK (0x20)
#define CPU_SCR0_PORS_MASK (0x10)
#define CPU_SCR0_SLEEP_MASK (0x08)
#define CPU_SCR0_STOP_MASK (0x01)
//=============================================================================
//=============================================================================
// Register Space, Bank 1
//=============================================================================
//=============================================================================
//-----------------------------------------------
// Port Registers
// Note: Also see this address range in Bank 0.
//-----------------------------------------------
// Port 0
#pragma ioport PRT0DM0: 0x100 // Port 0 Drive Mode 0
BYTE PRT0DM0;
#pragma ioport PRT0DM1: 0x101 // Port 0 Drive Mode 1
BYTE PRT0DM1;
#pragma ioport PRT0IC0: 0x102 // Port 0 Interrupt Control 0
BYTE PRT0IC0;
#pragma ioport PRT0IC1: 0x103 // Port 0 Interrupt Control 1
BYTE PRT0IC1;
// Port 1
#pragma ioport PRT1DM0: 0x104 // Port 1 Drive Mode 0
BYTE PRT1DM0;
#pragma ioport PRT1DM1: 0x105 // Port 1 Drive Mode 1
BYTE PRT1DM1;
#pragma ioport PRT1IC0: 0x106 // Port 1 Interrupt Control 0
BYTE PRT1IC0;
#pragma ioport PRT1IC1: 0x107 // Port 1 Interrupt Control 1
BYTE PRT1IC1;
// Port 2
#pragma ioport PRT2DM0: 0x108 // Port 2 Drive Mode 0
BYTE PRT2DM0;
#pragma ioport PRT2DM1: 0x109 // Port 2 Drive Mode 1
BYTE PRT2DM1;
#pragma ioport PRT2IC0: 0x10A // Port 2 Interrupt Control 0
BYTE PRT2IC0;
#pragma ioport PRT2IC1: 0x10B // Port 2 Interrupt Control 1
BYTE PRT2IC1;
// Port 3
#pragma ioport PRT3DM0: 0x10C // Port 3 Drive Mode 0
BYTE PRT3DM0;
#pragma ioport PRT3DM1: 0x10D // Port 3 Drive Mode 1
BYTE PRT3DM1;
#pragma ioport PRT3IC0: 0x10E // Port 3 Interrupt Control 0
BYTE PRT3IC0;
#pragma ioport PRT3IC1: 0x10F // Port 3 Interrupt Control 1
BYTE PRT3IC1;
// Port 4
#pragma ioport PRT4DM0: 0x110 // Port 4 Drive Mode 0
BYTE PRT4DM0;
#pragma ioport PRT4DM1: 0x111 // Port 4 Drive Mode 1
BYTE PRT4DM1;
#pragma ioport PRT4IC0: 0x112 // Port 4 Interrupt Control 0
BYTE PRT4IC0;
#pragma ioport PRT4IC1: 0x113 // Port 4 Interrupt Control 1
BYTE PRT4IC1;
// Port 5
#pragma ioport PRT5DM0: 0x114 // Port 5 Drive Mode 0
BYTE PRT5DM0;
#pragma ioport PRT5DM1: 0x115 // Port 5 Drive Mode 1
BYTE PRT5DM1;
#pragma ioport PRT5IC0: 0x116 // Port 5 Interrupt Control 0
BYTE PRT5IC0;
#pragma ioport PRT5IC1: 0x117 // Port 5 Interrupt Control 1
BYTE PRT5IC1;
//-----------------------------------------------
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