📄 m8c.h
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//=============================================================================
//
// m8c.h: M8C27000 Microcontroller Family System Declarations
//
// Copyright: Cypress MicroSystems 2003-2004. All Rights Reserved.
//
//
// This file provides address constants, bit field masks and a set of macro
// facilities for the Cypress MicroSystems 27xxx Microcontroller families.
//
// Last Modified: August 2, 2004
//
//=============================================================================
#ifndef M8C_C_HEADER
#define M8C_C_HEADER
//-----------------------------------------------
// Define System Types
//-----------------------------------------------
typedef unsigned char BOOL;
typedef unsigned char BYTE;
typedef signed char CHAR;
typedef unsigned int WORD;
typedef signed int INT;
typedef unsigned long DWORD;
typedef signed long LONG;
//-----------------------------------------------
// Define Boolean TRUE/FALSE
//-----------------------------------------------
#define TRUE ((BOOL) 1)
#define FALSE ((BOOL) 0)
//=============================================================================
//=============================================================================
// System Registers
//=============================================================================
//=============================================================================
//-----------------------------------------------
// Flag Register Bit Fields
//-----------------------------------------------
#define FLAG_XIO_MASK (0x10)
#define FLAG_SUPER (0x08)
#define FLAG_CARRY (0x04)
#define FLAG_ZERO (0x02)
#define FLAG_GLOBAL_IE (0x01)
//=============================================================================
//=============================================================================
// Register Space, Bank 0
//=============================================================================
//=============================================================================
//-----------------------------------------------
// Port Registers
// Note: Also see this address range in Bank 1.
//-----------------------------------------------
// Port 0
#pragma ioport PRT0DR: 0x000 // Port 0 Data Register
BYTE PRT0DR;
#pragma ioport PRT0IE: 0x001 // Port 0 Interrupt Enable Register
BYTE PRT0IE;
#pragma ioport PRT0GS: 0x002 // Port 0 Global Select Register
BYTE PRT0GS;
#pragma ioport PRT0DM2: 0x003 // Port 0 Drive Mode 2
BYTE PRT0DM2;
// Port 1
#pragma ioport PRT1DR: 0x004 // Port 1 Data Register
BYTE PRT1DR;
#pragma ioport PRT1IE: 0x005 // Port 1 Interrupt Enable Register
BYTE PRT1IE;
#pragma ioport PRT1GS: 0x006 // Port 1 Global Select Register
BYTE PRT1GS;
#pragma ioport PRT1DM2: 0x007 // Port 1 Drive Mode 2
BYTE PRT1DM2;
// Port 2
#pragma ioport PRT2DR: 0x008 // Port 2 Data Register
BYTE PRT2DR;
#pragma ioport PRT2IE: 0x009 // Port 2 Interrupt Enable Register
BYTE PRT2IE;
#pragma ioport PRT2GS: 0x00A // Port 2 Global Select Register
BYTE PRT2GS;
#pragma ioport PRT2DM2: 0x00B // Port 2 Drive Mode 2
BYTE PRT2DM2;
// Port 3
#pragma ioport PRT3DR: 0x00C // Port 3 Data Register
BYTE PRT3DR;
#pragma ioport PRT3IE: 0x00D // Port 3 Interrupt Enable Register
BYTE PRT3IE;
#pragma ioport PRT3GS: 0x00E // Port 3 Global Select Register
BYTE PRT3GS;
#pragma ioport PRT3DM2: 0x00F // Port 3 Drive Mode 2
BYTE PRT3DM2;
// Port 4
#pragma ioport PRT4DR: 0x010 // Port 4 Data Register
BYTE PRT4DR;
#pragma ioport PRT4IE: 0x011 // Port 4 Interrupt Enable Register
BYTE PRT4IE;
#pragma ioport PRT4GS: 0x012 // Port 4 Global Select Register
BYTE PRT4GS;
#pragma ioport PRT4DM2: 0x013 // Port 4 Drive Mode 2
BYTE PRT4DM2;
// Port 5
#pragma ioport PRT5DR: 0x014 // Port 5 Data Register
BYTE PRT5DR;
#pragma ioport PRT5IE: 0x015 // Port 5 Interrupt Enable Register
BYTE PRT5IE;
#pragma ioport PRT5GS: 0x016 // Port 5 Global Select Register
BYTE PRT5GS;
#pragma ioport PRT5DM2: 0x017 // Port 5 Drive Mode 2
BYTE PRT5DM2;
//-----------------------------------------------
// Digital PSoC(tm) block Registers
// Note: Also see this address range in Bank 1.
//-----------------------------------------------
// Digital PSoC block 00, Basic Type B
#pragma ioport DBB00DR0: 0x020 // data register 0
BYTE DBB00DR0;
#pragma ioport DBB00DR1: 0x021 // data register 1
BYTE DBB00DR1;
#pragma ioport DBB00DR2: 0x022 // data register 2
BYTE DBB00DR2;
#pragma ioport DBB00CR0: 0x023 // control & status register 0
BYTE DBB00CR0;
// Digital PSoC block 01, Basic Type B
#pragma ioport DBB01DR0: 0x024 // data register 0
BYTE DBB01DR0;
#pragma ioport DBB01DR1: 0x025 // data register 1
BYTE DBB01DR1;
#pragma ioport DBB01DR2: 0x026 // data register 2
BYTE DBB01DR2;
#pragma ioport DBB01CR0: 0x027 // control & status register 0
BYTE DBB01CR0;
// Digital PSoC block 02, Communication Type B
#pragma ioport DCB02DR0: 0x028 // data register 0
BYTE DCB02DR0;
#pragma ioport DCB02DR1: 0x029 // data register 1
BYTE DCB02DR1;
#pragma ioport DCB02DR2: 0x02A // data register 2
BYTE DCB02DR2;
#pragma ioport DCB02CR0: 0x02B // control & status register 0
BYTE DCB02CR0;
// Digital PSoC block 03, Communication Type B
#pragma ioport DCB03DR0: 0x02C // data register 0
BYTE DCB03DR0;
#pragma ioport DCB03DR1: 0x02D // data register 1
BYTE DCB03DR1;
#pragma ioport DCB03DR2: 0x02E // data register 2
BYTE DCB03DR2;
#pragma ioport DCB03CR0: 0x02F // control & status register 0
BYTE DCB03CR0;
// Digital PSoC block 10, Basic Type B
#pragma ioport DBB10DR0: 0x030 // data register 0
BYTE DBB10DR0;
#pragma ioport DBB10DR1: 0x031 // data register 1
BYTE DBB10DR1;
#pragma ioport DBB10DR2: 0x032 // data register 2
BYTE DBB10DR2;
#pragma ioport DBB10CR0: 0x033 // control & status register 0
BYTE DBB10CR0;
// Digital PSoC block 11, Basic Type B
#pragma ioport DBB11DR0: 0x034 // data register 0
BYTE DBB11DR0;
#pragma ioport DBB11DR1: 0x035 // data register 1
BYTE DBB11DR1;
#pragma ioport DBB11DR2: 0x036 // data register 2
BYTE DBB11DR2;
#pragma ioport DBB11CR0: 0x037 // control & status register 0
BYTE DBB11CR0;
// Digital PSoC block 12, Communications Type B
#pragma ioport DCB12DR0: 0x038 // data register 0
BYTE DCB12DR0;
#pragma ioport DCB12DR1: 0x039 // data register 1
BYTE DCB12DR1;
#pragma ioport DCB12DR2: 0x03A // data register 2
BYTE DCB12DR2;
#pragma ioport DCB12CR0: 0x03B // control & status register 0
BYTE DCB12CR0;
// Digital PSoC block 13, Communications Type B
#pragma ioport DCB13DR0: 0x03C // data register 0
BYTE DCB13DR0;
#pragma ioport DCB13DR1: 0x03D // data register 1
BYTE DCB13DR1;
#pragma ioport DCB13DR2: 0x03E // data register 2
BYTE DCB13DR2;
#pragma ioport DCB13CR0: 0x03F // control & status register 0
BYTE DCB13CR0;
//-----------------------------------------------
// Analog Resource Control Registers
//-----------------------------------------------
#pragma ioport AMX_IN: 0x060 // Analog Input Multiplexor Control
BYTE AMX_IN;
#define AMX_IN_ACI3 (0xC0)
#define AMX_IN_ACI2 (0x30)
#define AMX_IN_ACI1 (0x0C)
#define AMX_IN_ACI0 (0x03)
#pragma ioport ARF_CR: 0x063 // Analog Reference Control Register
BYTE ARF_CR;
#define ARF_CR_HBE (0x40)
#define ARF_CR_REF (0x38)
#define ARF_CR_REFPWR (0x07)
#define ARF_CR_SCPWR (0x03)
// Deprecated:
#define ARF_CR_APWR (0x04)
#pragma ioport CMP_CR0: 0x064 // Analog Comparator Bus Register 0
BYTE CMP_CR0;
#define CMP_CR0_COMP3 (0x80)
#define CMP_CR0_COMP2 (0x40)
#define CMP_CR0_COMP1 (0x20)
#define CMP_CR0_COMP0 (0x10)
#define CMP_CR0_AINT3 (0x08)
#define CMP_CR0_AINT2 (0x04)
#define CMP_CR0_AINT1 (0x02)
#define CMP_CR0_AINT0 (0x01)
#pragma ioport ASY_CR: 0x065 // Analog Synchronizaton Control Register
BYTE ASY_CR;
#define ASY_CR_SARCOUNT (0x70)
#define ASY_CR_SARSIGN (0x08)
#define ASY_CR_SARCOL (0x06)
#define ASY_CR_SYNCEN (0x01)
#pragma ioport CMP_CR1: 0x66 // Analog Comparator Bus Register 1
BYTE CMP_CR1;
#define CMP_CR1_ASYNCH3 (0x80)
#define CMP_CR1_ASYNCH2 (0x40)
#define CMP_CR1_ASYNCH1 (0x20)
#define CMP_CR1_ASYNCH0 (0x10)
//-----------------------------------------------
// Analog PSoC block Registers
//
// Note: the following registers are mapped into
// both register bank 0 AND register bank 1.
//-----------------------------------------------
// Continuous Time PSoC Block Type B Row 0 Col 0
#pragma ioport ACB00CR3: 0x070 // Control register 3
BYTE ACB00CR3;
#pragma ioport ACB00CR0: 0x071 // Control register 0
BYTE ACB00CR0;
#pragma ioport ACB00CR1: 0x072 // Control register 1
BYTE ACB00CR1;
#pragma ioport ACB00CR2: 0x073 // Control register 2
BYTE ACB00CR2;
// Continuous Time PSoC Block Type B Row 0 Col 1
#pragma ioport ACB01CR3: 0x074 // Control register 3
BYTE ACB01CR3;
#pragma ioport ACB01CR0: 0x075 // Control register 0
BYTE ACB01CR0;
#pragma ioport ACB01CR1: 0x076 // Control register 1
BYTE ACB01CR1;
#pragma ioport ACB01CR2: 0x077 // Control register 2
BYTE ACB01CR2;
// Continuous Time PSoC Block Type B Row 0 Col 2
#pragma ioport ACB02CR3: 0x078 // Control register 3
BYTE ACB02CR3;
#pragma ioport ACB02CR0: 0x079 // Control register 0
BYTE ACB02CR0;
#pragma ioport ACB02CR1: 0x07A // Control register 1
BYTE ACB02CR1;
#pragma ioport ACB02CR2: 0x07B // Control register 2
BYTE ACB02CR2;
// Continuous Time PSoC Block Type B Row 0 Col 3
#pragma ioport ACB03CR3: 0x07C // Control register 3
BYTE ACB03CR3;
#pragma ioport ACB03CR0: 0x07D // Control register 0
BYTE ACB03CR0;
#pragma ioport ACB03CR1: 0x07E // Control register 1
BYTE ACB03CR1;
#pragma ioport ACB03CR2: 0x07F // Control register 2
BYTE ACB03CR2;
// Switched Cap PSoC Block Type C Row 1 Col 0
#pragma ioport ASC10CR0: 0x080 // Control register 0
BYTE ASC10CR0;
#pragma ioport ASC10CR1: 0x081 // Control register 1
BYTE ASC10CR1;
#pragma ioport ASC10CR2: 0x082 // Control register 2
BYTE ASC10CR2;
#pragma ioport ASC10CR3: 0x083 // Control register 3
BYTE ASC10CR3;
// Switched Cap PSoC Block Type D Row 1 Col 1
#pragma ioport ASD11CR0: 0x084 // Control register 0
BYTE ASD11CR0;
#pragma ioport ASD11CR1: 0x085 // Control register 1
BYTE ASD11CR1;
#pragma ioport ASD11CR2: 0x086 // Control register 2
BYTE ASD11CR2;
#pragma ioport ASD11CR3: 0x087 // Control register 3
BYTE ASD11CR3;
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