📄 adcinc14int.lis
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0000 ; Power Settings
0003 ADCINC14_bfPOWERMASK: equ 03h
0000 ADCINC14_OFF: equ 00h
0001 ADCINC14_LOWPOWER: equ 01h
0002 ADCINC14_MEDPOWER: equ 02h
0003 ADCINC14_HIGHPOWER: equ 03h
0000
0000 ; Parameter Settings
0001 ADCINC14_CALCTIME: equ 1h
0008 ADCINC14_fCOMPARE_TRUE: equ 08h ; Bit to enable compare True interrupts
0000
0000 ; Functionality constants
0010 ADCINC14_fFSW0: equ 10h ; Switch Cap FSW0 switch enable
0001 ADCINC14_NoAZ: equ 01h ; Set if AutoZero is no enabled
0020 ADCINC14_fAutoZero: equ 20h ; Switch Cap AutoZero switch enable
0001 ADCINC14_fDBLK_ENABLE: equ 01h ; Digital block enable bit
0004 ADCINC14_fPULSE_WIDE: equ 04h ; Use full clock width pulse.
0000
0000 ; fStatus definitions
0001 ADCINC14_fDATA_READY: equ 01h ; This bit is set when data is available
0000
0000 ; Data Format
0000 ADCINC14_DATA_FORMAT: equ 0
0000
0000 ;--------------------------------------------------
0000 ; Register Address Constants for ADCINC14
0000 ;--------------------------------------------------
0000 ; ADCINC14 PSoC Block register Definitions
0000 ; Integrator Block Register Definitions
0084 ADCINC14_bfAtoDcr0: equ 84h
0085 ADCINC14_bfAtoDcr1: equ 85h
0086 ADCINC14_bfAtoDcr2: equ 86h
0087 ADCINC14_bfAtoDcr3: equ 87h
0000
0000 ; Counter Block Register Definitions
0030 ADCINC14_fCounterFN: equ 30h
0031 ADCINC14_fCounterSL: equ 31h
0032 ADCINC14_fCounterOS: equ 32h
0030 ADCINC14_bCount: equ 30h
0031 ADCINC14_bPeriod: equ 31h
0032 ADCINC14_bCompare: equ 32h
0033 ADCINC14_bCounter_CR0: equ 33h
0000
0000 ; PWM24 Block Register Definitions
0034 ADCINC14_bfPWM_LSB_FN: equ 34h
0038 ADCINC14_bfPWM_ISB_FN: equ 38h
003C ADCINC14_bfPWM_MSB_FN: equ 3ch
0037 ADCINC14_fPWM_LSB_CR0: equ 37h
003B ADCINC14_fPWM_ISB_CR0: equ 3bh
003F ADCINC14_fPWM_MSB_CR0: equ 3fh
0034 ADCINC14_bPWM_Count_LSB: equ 34h
0038 ADCINC14_bPWM_Count_ISB: equ 38h
003C ADCINC14_bPWM_Count_MSB: equ 3ch
0035 ADCINC14_bPWM_Period_LSB: equ 35h
0039 ADCINC14_bPWM_Period_ISB: equ 39h
003D ADCINC14_bPWM_Period_MSB: equ 3dh
0036 ADCINC14_bPWM_IntTime_LSB: equ 36h
003A ADCINC14_bPWM_IntTime_ISB: equ 3ah
003E ADCINC14_bPWM_IntTime_MSB: equ 3eh
0034 ADCINC14_bfPWM_LSB_FN: equ 34h
0038 ADCINC14_bfPWM_ISB_FN: equ 38h
003C ADCINC14_bfPWM_MSB_FN: equ 3ch
0000
0000
0000 ; end of file ADCINC14.inc
0000
0000
0000 ;-----------------------------------------------
0000 ; Global Symbols
0000 ;-----------------------------------------------
export _ADCINC14_CNT_ISR
export _ADCINC14_PWM24_ISR
export ADCINC14_iCounterU
export _ADCINC14_iResult
export ADCINC14_iResult
export _ADCINC14_bfStatus
export ADCINC14_bfStatus
export ADCINC14_bSampC
;-----------------------------------------------
; Variable Allocation
;-----------------------------------------------
AREA InterruptRAM(RAM, REL, CON)
0000 ADCINC14_iCounterU: BLK 2 ;The Upper word of the Counter
0002 _ADCINC14_iResult:
0002 ADCINC14_iResult: BLK 2 ;A/D value
0004 _ADCINC14_bfStatus:
0004 ADCINC14_bfStatus: BLK 1 ;Data Valid Flag
0005 ADCINC14_bSampC: BLK 1 ;# of times to run A/D
0006
0006
0006 ;-----------------------------------------------
0006 ; EQUATES and TABLES
0006 ;-----------------------------------------------
0001 LSB: equ 1
0000 MSB: equ 0
0006
0006 ;@PSoC_UserCode_INIT@ (Do not change this line.)
0006 ;---------------------------------------------------
0006 ; Insert your custom declarations below this banner
0006 ;---------------------------------------------------
0006
0006 ;------------------------
0006 ; Includes
0006 ;------------------------
0006
0006
0006 ;------------------------
0006 ; Constant Definitions
0006 ;------------------------
0006
0006
0006 ;------------------------
0006 ; Variable Allocation
0006 ;------------------------
0006
0006
0006 ;---------------------------------------------------
0006 ; Insert your custom declarations above this banner
0006 ;---------------------------------------------------
0006 ;@PSoC_UserCode_END@ (Do not change this line.)
0006
0006
AREA UserModules (ROM, REL)
;-----------------------------------------------------------------------------
; FUNCTION NAME: ADCINC14_CNT_ISR (Counter8 Interrupt)
;
;
; DESCRIPTION:
; Increment the upper (software) half on the counter whenever the
; lower (hardware) half of the counter underflows. This counter
; should start out at the most negative value (0xFF).
;
;-----------------------------------------------------------------------------
;
0000 _ADCINC14_CNT_ISR:
0000 7601 inc [ADCINC14_iCounterU+LSB]
0002 D003 jnc END_ADCINC14_CNT_ISR
0004 7600 inc [ADCINC14_iCounterU+MSB]
0006
0006 ;@PSoC_UserCode_BODY_1@ (Do not change this line.)
0006 ;---------------------------------------------------
0006 ; Insert your custom code below this banner
0006 ;---------------------------------------------------
0006 ; NOTE: interrupt service routines must preserve
0006 ; the values of the A and X CPU registers.
0006
0006 ;---------------------------------------------------
0006 ; Insert your custom code above this banner
0006 ;---------------------------------------------------
0006 ;@PSoC_UserCode_END@ (Do not change this line.)
0006
0006 END_ADCINC14_CNT_ISR:
0006 7E reti
0007
0007
0007 ;-----------------------------------------------------------------------------
0007 ; FUNCTION NAME: ADCINC14_PWM24_ISR (PWM24 Interrupt)
0007 ;
0007 ; DESCRIPTION:
0007 ; This ISR is called when the ADC has completed and integrate cycle.
0007 ; The ADC value is calculated and stored in a global location before
0007 ; the end of the ISR.
0007 ;
0007 ;-----------------------------------------------------------------------------
0007 ;
0007 ; SIDE EFFECTS:
0007 ;
0007 ; THEORY of OPERATION or PROCEDURE:
0007 ;
0007 ;-----------------------------------------------------------------------------
0007 _ADCINC14_PWM24_ISR:
0007 4133FE and reg[ADCINC14_bCounter_CR0], ~ADCINC14_fDBLK_ENABLE ; Disable Counter
IF ADCINC14_NoAZ
000A 438620 or reg[ADCINC14_bfAtoDcr2], ADCINC14_fAutoZero ; Put Integrator in AutoZero
ENDIF
000D 438710 or reg[ADCINC14_bfAtoDcr3],ADCINC14_fFSW0 ; Put Integrator in reset
0010
0010 ; Enable interrupts for a short period of time just in case.
0010 ; Make sure we didn't have a counter interrupt ready to fire
0010 7101 or F, FLAG_GLOBAL_IE
0012 40 nop ; Wait a couple cycles
0013 70FE and F, ~FLAG_GLOBAL_IE
0015 08 push A ; Save the Accumulator
0016 5D30 mov A,reg[ADCINC14_bCount] ; Read counter value (Bogus read puts value in Period register)
0018 5D32 mov A,reg[ADCINC14_bCompare] ; Read counter value
001A 78 dec A ; Decrement by one to make sure we didn't miss a count
001B 73 cpl A ; Invert the value
001C D007 jnc .INT_CALCV ; if carry, then inc MSB as well
001E 7601 inc [ADCINC14_iCounterU + LSB]
0020 D003 jnc .INT_CALCV ; if carry, then inc MSB as well
0022 7600 inc [ADCINC14_iCounterU + MSB]
0024 .INT_CALCV:
0024 5303 mov [(ADCINC14_iResult + LSB)], A ; Store LSB value
0026 5101 mov A, [ADCINC14_iCounterU + LSB] ; Store MSB from temp counter
0028 5302 mov [(ADCINC14_iResult + MSB)], A
002A ; The new value has been stored,
002A ; so get counters ready for next reading first.
002A 6231FF mov reg[ADCINC14_bPeriod],0xFF ⌨️ 快捷键说明
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