📄 pwm16.lis
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0000
00DF OSC_CR3: equ DFh ; Oscillator Control Register 3 (RW)
0000
00E0 OSC_CR0: equ E0h ; System Oscillator Control Register 0 (RW)
0080 OSC_CR0_32K_SELECT: equ 80h ; MASK: Enable/Disable External XTAL Osc
0040 OSC_CR0_PLL_MODE: equ 40h ; MASK: Enable/Disable PLL
0020 OSC_CR0_NO_BUZZ: equ 20h ; MASK: Bandgap always powered/BUZZ bandgap
0018 OSC_CR0_SLEEP: equ 18h ; MASK: Set Sleep timer freq/period
0000 OSC_CR0_SLEEP_512Hz: equ 00h ; Set sleep bits for 1.95ms period
0008 OSC_CR0_SLEEP_64Hz: equ 08h ; Set sleep bits for 15.6ms period
0010 OSC_CR0_SLEEP_8Hz: equ 10h ; Set sleep bits for 125ms period
0018 OSC_CR0_SLEEP_1Hz: equ 18h ; Set sleep bits for 1 sec period
0007 OSC_CR0_CPU: equ 07h ; MASK: Set CPU Frequency
0000 OSC_CR0_CPU_3MHz: equ 00h ; set CPU Freq bits for 3MHz Operation
0001 OSC_CR0_CPU_6MHz: equ 01h ; set CPU Freq bits for 6MHz Operation
0002 OSC_CR0_CPU_12MHz: equ 02h ; set CPU Freq bits for 12MHz Operation
0003 OSC_CR0_CPU_24MHz: equ 03h ; set CPU Freq bits for 24MHz Operation
0004 OSC_CR0_CPU_1d5MHz: equ 04h ; set CPU Freq bits for 1.5MHz Operation
0005 OSC_CR0_CPU_750kHz: equ 05h ; set CPU Freq bits for 750kHz Operation
0006 OSC_CR0_CPU_187d5kHz: equ 06h ; set CPU Freq bits for 187.5kHz Operation
0007 OSC_CR0_CPU_93d7kHz: equ 07h ; set CPU Freq bits for 93.7kHz Operation
0000
00E1 OSC_CR1: equ E1h ; System VC1/VC2 Divider Control Register (RW)
00F0 OSC_CR1_VC1: equ F0h ; MASK: System VC1 24MHz/External Clk divider
000F OSC_CR1_VC2: equ 0Fh ; MASK: System VC2 24MHz/External Clk divider
0000
00E2 OSC_CR2: equ E2h ; Oscillator Control Register 2 (RW)
0080 OSC_CR2_PLLGAIN: equ 80h ; MASK: High/Low gain
0004 OSC_CR2_EXTCLKEN: equ 04h ; MASK: Enable/Disable External Clock
0002 OSC_CR2_IMODIS: equ 02h ; MASK: Enable/Disable System (IMO) Clock Net
0001 OSC_CR2_SYSCLKX2DIS: equ 01h ; MASK: Enable/Disable 48MHz clock source
0000
00E3 VLT_CR: equ E3h ; Voltage Monitor Control Register (RW)
0080 VLT_CR_SMP: equ 80h ; MASK: Enable Switch Mode Pump
0030 VLT_CR_PORLEV: equ 30h ; MASK: Mask for Power on Reset level control
0000 VLT_CR_POR_LOW: equ 00h ; Lowest Precision Power-on Reset trip point
0010 VLT_CR_POR_MID: equ 10h ; Middle Precision Power-on Reset trip point
0020 VLT_CR_POR_HIGH: equ 20h ; Highest Precision Power-on Reset trip point
0008 VLT_CR_LVDTBEN: equ 08h ; MASK: Enable the CPU Throttle Back on LVD
0007 VLT_CR_VM: equ 07h ; MASK: Mask for Voltage Monitor level setting
0000 VLT_CR_3V0_POR: equ 00h ; -- deprecated symbols --
0010 VLT_CR_4V5_POR: equ 10h ; deprecated
0020 VLT_CR_4V75_POR: equ 20h ; deprecated
0030 VLT_CR_DISABLE: equ 30h ; deprecated
0000
00E4 VLT_CMP: equ E4h ; Voltage Monitor Comparators Register (R)
0008 VLT_CMP_PUMP: equ 08h ; MASK: Vcc below SMP trip level
0008 VLT_CMP_LVD: equ 08h ; MASK: Vcc below LVD trip level
0008 VLT_CMP_PPOR: equ 08h ; MASK: Vcc below PPOR trip level
0000
00E8 IMO_TR: equ E8h ; Internal Main Oscillator Trim Register (W)
00E9 ILO_TR: equ E9h ; Internal Low-speed Oscillator Trim (W)
00EA BDG_TR: equ EAh ; Band Gap Trim Register (W)
00EB ECO_TR: equ EBh ; External Oscillator Trim Register (W)
0000
0000 ;;=============================================================================
0000 ;; M8C System Macros
0000 ;; These macros should be used when their functions are needed.
0000 ;;=============================================================================
0000
0000 ;----------------------------------------------------
0000 ; Swapping Register Banks
0000 ;----------------------------------------------------
0000 macro M8C_SetBank0
0000 and F, ~FLAG_XIO_MASK
0000 macro M8C_SetBank1
0000 or F, FLAG_XIO_MASK
0000 macro M8C_EnableGInt
0000 or F, FLAG_GLOBAL_IE
0000 macro M8C_DisableGInt
0000 and F, ~FLAG_GLOBAL_IE
0000 macro M8C_DisableIntMask
0000 and reg[@0], ~@1 ; disable specified interrupt enable bit
0000 macro M8C_EnableIntMask
0000 or reg[@0], @1 ; enable specified interrupt enable bit
0000 macro M8C_ClearIntFlag
0000 mov reg[@0], ~@1 ; clear specified interrupt enable bit
0000 macro M8C_EnableWatchDog
0000 and reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
0000 macro M8C_ClearWDT
0000 mov reg[RES_WDT], 00h
0000 macro M8C_ClearWDTAndSleep
0000 mov reg[RES_WDT], 38h
0000 macro M8C_Stall
0000 or reg[ASY_CR], ASY_CR_SYNCEN
0000 macro M8C_Unstall
0000 and reg[ASY_CR], ~ASY_CR_SYNCEN
0000 macro M8C_Sleep
0000 or reg[CPU_SCR0], CPU_SCR0_SLEEP_MASK
0000 ; The next instruction to be executed depends on the state of the
0000 ; various interrupt enable bits. If some interrupts are enabled
0000 ; and the global interrupts are disabled, the next instruction will
0000 ; be the one that follows the invocation of this macro. If global
0000 ; interrupts are also enabled then the next instruction will be
0000 ; from the interrupt vector table. If no interrupts are enabled
0000 ; then the CPU sleeps forever.
0000 macro M8C_Stop
0000 ; In general, you probably don't want to do this, but here's how:
0000 or reg[CPU_SCR0], CPU_SCR0_STOP_MASK
0000 ; Next instruction to be executed is located in the interrupt
0000 ; vector table entry for Power-On Reset.
0000 macro M8C_Reset
0000 ; Restore CPU to the power-on reset state.
0000 mov A, 0
0000 SSC
0000 ; Next non-supervisor instruction will be at interrupt vector 0.
0000 macro Suspend_CodeCompressor
0000 or F, 0
0000 macro Resume_CodeCompressor
0000 add SP, 0
0010 FLAG_XIO_MASK: equ 10h
0008 FLAG_SUPER: equ 08h
0004 FLAG_CARRY: equ 04h
0002 FLAG_ZERO: equ 02h
0001 FLAG_GLOBAL_IE: equ 01h
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
0013 PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
0017 PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 02, Communications Type B
0028 DCB02DR0: equ 28h ; data register 0 (#)
0029 DCB02DR1: equ 29h ; data register 1 (W)
002A DCB02DR2: equ 2Ah ; data register 2 (RW)
002B DCB02CR0: equ 2Bh ; control & status register 0 (#)
0000
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