📄 psocconfig.lis
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0000 IF ( @ACTUAL_CLASS & RAM_USE_CLASS_4 )
0000 ; Nothing to do
0000 ENDIF ; RAM_USE_CLASS_4
0000
0000 macro REG_PRESERVE( IOReg )
0000 mov A, reg[ @IOReg ]
0000 push A
0000 macro REG_RESTORE( IOReg )
0000 pop A
0000 mov reg[ @IOReg ], A
0000 macro ISR_PRESERVE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_PRESERVE PRV_PP
0000 REG_PRESERVE CUR_PP
0000 REG_PRESERVE IDX_PP
0000 REG_PRESERVE MVR_PP
0000 REG_PRESERVE MVW_PP
0000 ENDIF
0000 macro ISR_RESTORE_PAGE_POINTERS
0000 IF ( SYSTEM_LARGE_MEMORY_MODEL )
0000 REG_RESTORE MVW_PP
0000 REG_RESTORE MVR_PP
0000 REG_RESTORE IDX_PP
0000 REG_RESTORE CUR_PP
0000 REG_RESTORE PRV_PP
0000 ENDIF
0003 CPU_CLOCK: equ 3h ;CPU clock value
0007 CPU_CLOCK_MASK: equ 7h ;CPU clock mask
0003 CPU_CLOCK_JUST: equ 3h ;CPU clock value justified
0000 SELECT_32K: equ 0h ;32K select value
0080 SELECT_32K_MASK: equ 80h ;32K select mask
0000 SELECT_32K_JUST: equ 0h ;32K select value justified
0000 PLL_MODE: equ 0h ;PLL mode value
0040 PLL_MODE_MASK: equ 40h ;PLL mode mask
0000 PLL_MODE_JUST: equ 0h ;PLL mode value justified
0003 SLEEP_TIMER: equ 3h ;Sleep Timer value
0018 SLEEP_TIMER_MASK: equ 18h ;Sleep Timer mask
0018 SLEEP_TIMER_JUST: equ 18h ;Sleep Timer value justified
0001 SWITCH_MODE_PUMP: equ 1h ;Switch Mode Pump setting
0080 SWITCH_MODE_PUMP_MASK: equ 80h ;Switch Mode Pump mask
0080 SWITCH_MODE_PUMP_JUST: equ 80h ;Switch Mode Pump justified
0000 LVD_TBEN: equ 0 ; Low Voltage Throttle-back enable value
0008 LVD_TBEN_MASK: equ 8 ; Low Voltage Throttle-back enable mask
0000 LVD_TBEN_JUST: equ 0 ; Low Voltage Throttle-back enable justified
0007 TRIP_VOLTAGE: equ 7h ;Trip Voltage value
0007 TRIP_VOLTAGE_MASK: equ 7h ;Trip Voltage mask
0007 TRIP_VOLTAGE_JUST: equ 7h ;Trip Voltage justified
0001 SUPPLY_VOLTAGE: equ 1h ;Supply Voltage 1 = 5.0V, 0 = 3.3V
0000
0010 POWER_SET_5V0: equ 10h ; MASK for 5.0V operation, fast and slow
0010 POWER_SET_5V0_24MHZ: equ 10h ; Power Setting value for 5.0V fast
0011 POWER_SET_5V0_6MHZ: equ 11h ; Power Setting value for 5.0V slow
0008 POWER_SET_3V3: equ 08h ; MASK for 3.3V operation, fast and slow
0008 POWER_SET_3V3_24MHZ: equ 08h ; Power Setting value for 3.3V fast
0009 POWER_SET_3V3_6MHZ: equ 09h ; Power Setting value for 3.3V slow
0006 POWER_SET_2V7: equ 06h ; MASK for 2.7V operation, fast and slow
0004 POWER_SET_2V7_12MHZ: equ 04h ; MASK for 2.7V, 12MHZ operation
0002 POWER_SET_2V7_6MHZ: equ 02h ; MASK for 2.7V, 6MHZ operation
0001 POWER_SET_SLOW_IMO: equ 01h ; MASK for slow Internal Main Oscillator (IMO)
0000
0000 COMM_RX_PRESENT: equ 0 ;1 = TRUE
0000 WATCHDOG_ENABLE: equ 0 ;Watchdog Enable 1 = Enable
0000
0003 CLOCK_DIV_VC1: equ 3h ;VC1 clock divider
00F0 CLOCK_DIV_VC1_MASK: equ f0h ;VC1 clock divider mask
0030 CLOCK_DIV_VC1_JUST: equ 30h ;VC1 clock divider justified
0005 CLOCK_DIV_VC2: equ 5h ;VC2 clock divider
000F CLOCK_DIV_VC2_MASK: equ fh ;VC2 clock divider mask
0005 CLOCK_DIV_VC2_JUST: equ 5h ;VC2 clock divider justified
0000 CLOCK_INPUT_VC3: equ 0h ;VC3 clock source
0003 CLOCK_INPUT_VC3_MASK: equ 3h ;VC3 clock source mask
0000 CLOCK_INPUT_VC3_JUST: equ 0h ;VC3 clock source justified
00FF CLOCK_DIV_VC3: equ ffh ;VC3 clock divider
00FF CLOCK_DIV_VC3_MASK: equ ffh ;VC3 clock divider mask
00FF CLOCK_DIV_VC3_JUST: equ ffh ;VC3 clock divider justified
0000 ANALOG_BUFFER_PWR: equ 0h ;Analog buffer power level
0001 ANALOG_BUFFER_PWR_MASK: equ 1h ;Analog buffer power level mask
0000 ANALOG_BUFFER_PWR_JUST: equ 0h ;Analog buffer power level justified
0005 ANALOG_POWER: equ 5h ;Analog power control
0007 ANALOG_POWER_MASK: equ 7h ;Analog power control mask
0005 ANALOG_POWER_JUST: equ 5h ;Analog power control justified
0000 OP_AMP_BIAS: equ 0h ;Op amp bias level
0040 OP_AMP_BIAS_MASK: equ 40h ;Op amp bias level mask
0000 OP_AMP_BIAS_JUST: equ 0h ;Op amp bias level justified
0000 REF_MUX: equ 0h ;Ref mux setting
0038 REF_MUX_MASK: equ 38h ;Ref mux setting mask
0000 REF_MUX_JUST: equ 0h ;Ref mux setting justified
0000 AGND_BYPASS: equ 0h ;AGndBypass setting
0040 AGND_BYPASS_MASK: equ 40h ;AGndBypass setting mask
0000 AGND_BYPASS_JUST: equ 0h ;AGndBypass setting justified
0000 SYSCLK_SOURCE: equ (0h | 0h) ;SysClk Source setting
0006 SYSCLK_SOURCE_MASK: equ (4h | 2h) ;SysClk Source setting mask
0000 SYSCLK_SOURCE_JUST: equ (0h | 0h) ;SysClk Source setting justified
0000 SYSCLK_2_DISABLE: equ 0h ;SysClk*2 Disable setting
0001 SYSCLK_2_DISABLE_MASK: equ 1h ;SysClk*2 Disable setting mask
0000 SYSCLK_2_DISABLE_JUST: equ 0h ;SysClk*2 Disable setting justified
0000 ;
0000 ; register initial values
0000 ;
0080 ANALOG_IO_CONTROL: equ 80h ;Analog IO Control register (ABF_CR)
0000 PORT_0_GLOBAL_SELECT: equ 0h ;Port 0 global select register (PRT0GS)
0000 PORT_0_DRIVE_0: equ 0h ;Port 0 drive mode 0 register (PRT0DM0)
00FF PORT_0_DRIVE_1: equ ffh ;Port 0 drive mode 1 register (PRT0DM1)
002B PORT_0_DRIVE_2: equ 2bh ;Port 0 drive mode 2 register (PRT0DM2)
0000 PORT_0_INTENABLE: equ 0h ;Port 0 interrupt enable register (PRT0IE)
0000 PORT_0_INTCTRL_0: equ 0h ;Port 0 interrupt control 0 register (PRT0IC0)
0000 PORT_0_INTCTRL_1: equ 0h ;Port 0 interrupt control 1 register (PRT0IC1)
0000 PORT_1_GLOBAL_SELECT: equ 0h ;Port 1 global select register (PRT1GS)
0000 PORT_1_DRIVE_0: equ 0h ;Port 1 drive mode 0 register (PRT1DM0)
00FF PORT_1_DRIVE_1: equ ffh ;Port 1 drive mode 1 register (PRT1DM1)
00FF PORT_1_DRIVE_2: equ ffh ;Port 1 drive mode 2 register (PRT1DM2)
0000 PORT_1_INTENABLE: equ 0h ;Port 1 interrupt enable register (PRT1IE)
0000 PORT_1_INTCTRL_0: equ 0h ;Port 1 interrupt control 0 register (PRT1IC0)
0000 PORT_1_INTCTRL_1: equ 0h ;Port 1 interrupt control 1 register (PRT1IC1)
0001 PORT_2_GLOBAL_SELECT: equ 1h ;Port 2 global select register (PRT2GS)
000F PORT_2_DRIVE_0: equ fh ;Port 2 drive mode 0 register (PRT2DM0)
00F0 PORT_2_DRIVE_1: equ f0h ;Port 2 drive mode 1 register (PRT2DM1)
00F0 PORT_2_DRIVE_2: equ f0h ;Port 2 drive mode 2 register (PRT2DM2)
0000 PORT_2_INTENABLE: equ 0h ;Port 2 interrupt enable register (PRT2IE)
0000 PORT_2_INTCTRL_0: equ 0h ;Port 2 interrupt control 0 register (PRT2IC0)
0000 PORT_2_INTCTRL_1: equ 0h ;Port 2 interrupt control 1 register (PRT2IC1)
0000 PORT_3_GLOBAL_SELECT: equ 0h ;Port 3 global select register (PRT3GS)
0000 PORT_3_DRIVE_0: equ 0h ;Port 3 drive mode 0 register (PRT3DM0)
0000 PORT_3_DRIVE_1: equ 0h ;Port 3 drive mode 1 register (PRT3DM1)
0000 PORT_3_DRIVE_2: equ 0h ;Port 3 drive mode 2 register (PRT3DM2)
0000 PORT_3_INTENABLE: equ 0h ;Port 3 interrupt enable register (PRT3IE)
0000 PORT_3_INTCTRL_0: equ 0h ;Port 3 interrupt control 0 register (PRT3IC0)
0000 PORT_3_INTCTRL_1: equ 0h ;Port 3 interrupt control 1 register (PRT3IC1)
0000 PORT_4_GLOBAL_SELECT: equ 0h ;Port 4 global select register (PRT4GS)
0000 PORT_4_DRIVE_0: equ 0h ;Port 4 drive mode 0 register (PRT4DM0)
0000 PORT_4_DRIVE_1: equ 0h ;Port 4 drive mode 1 register (PRT4DM1)
0000 PORT_4_DRIVE_2: equ 0h ;Port 4 drive mode 2 register (PRT4DM2)
0000 PORT_4_INTENABLE: equ 0h ;Port 4 interrupt enable register (PRT4IE)
0000 PORT_4_INTCTRL_0: equ 0h ;Port 4 interrupt control 0 register (PRT4IC0)
0000 PORT_4_INTCTRL_1: equ 0h ;Port 4 interrupt control 1 register (PRT4IC1)
0000 PORT_5_GLOBAL_SELECT: equ 0h ;Port 5 global select register (PRT5GS)
0000 PORT_5_DRIVE_0: equ 0h ;Port 5 drive mode 0 register (PRT5DM0)
0000 PORT_5_DRIVE_1: equ 0h ;Port 5 drive mode 1 register (PRT5DM1)
0000 PORT_5_DRIVE_2: equ 0h ;Port 5 drive mode 2 register (PRT5DM2)
0000 PORT_5_INTENABLE: equ 0h ;Port 5 interrupt enable register (PRT5IE)
0000 PORT_5_INTCTRL_0: equ 0h ;Port 5 interrupt control 0 register (PRT5IC0)
0000 PORT_5_INTCTRL_1: equ 0h ;Port 5 interrupt control 1 register (PRT5IC1)
0000
0000 ; end of file GlobalParams.inc
0000
export LoadConfigInit
export _LoadConfigInit
export LoadConfig_freq_occur_ad_to_pwm
export _LoadConfig_freq_occur_ad_to_pwm
export NO_SHADOW
export _NO_SHADOW
0010 FLAG_CFG_MASK: equ 10h ;M8C flag register REG address bit mask
00FF END_CONFIG_TABLE: equ ffh ;end of config table indicator
0000
AREA psoc_config(rom, rel)
;---------------------------------------------------------------------------
; LoadConfigInit - Establish the start-up configuration (except for a few
; parameters handled by boot code, like CPU speed). This
; function can be called from user code, but typically it
; is only called from boot.
;
; INPUTS: None.
; RETURNS: Nothing.
; SIDE EFFECTS: Registers are volatile: the A and X registers can be modified!
; In the large memory model currently only the page
; pointer registers listed below are modified. This does
; not guarantee that in future implementations of this
; function other page pointer registers will not be
; modified.
;
; Page Pointer Registers Modified:
; CUR_PP
;
0000 _LoadConfigInit:
0000 LoadConfigInit:
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_1 )
; Nothing to do
ENDIF ; RAM_USE_CLASS_1
IF ( RAM_USE_CLASS_4 & RAM_USE_CLASS_2 )
IF ( SYSTEM_IDXPG_TRACKS_IDX_PP )
IF ( SYSTEM_LARGE_MEMORY_MODEL )
or F, FLAG_PGMODE_01b
ENDIF ; SYSTEM_LARGE_MEMORY_MODEL
ENDIF
ENDIF ; RAM_USE_CLASS_2
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