up3_board.map.eqn

NIOSII 实验指导

P1L21 = P1L72 & !D1_i_read;


--P1L6 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|cpu_0_data_master_qualified_request_payload_buffer_s1~209
--operation mode is normal

P1L6 = W1_d_write & !P1L4 & (!P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register # !D1_d_read) # !W1_d_write & (!P1_cpu_0_data_master_read_data_valid_payload_buffer_s1_shift_register # !D1_d_read);


--P1L1 is UP3_Board:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1|always2~80
--operation mode is normal

P1L1 = P1L21 & P1_cpu_0_data_master_requests_payload_buffer_s1 & P1L6 & !P1_cpu_0_instruction_master_read_data_valid_payload_buffer_s1_shift_register;


--F1L01 is UP3_Board:inst|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master|cpu_0_instruction_master_waitrequest~71
--operation mode is normal

F1L01 = F1L8 & F1L9 & (!P1L1 # !P1_cpu_0_data_master_s_turn_at_payload_buffer_s1);


--S1_cfi_flash_0_s1_in_a_read_cycle is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_in_a_read_cycle
--operation mode is normal

S1_cfi_flash_0_s1_in_a_read_cycle = S1L13 # D1_d_read & S1L12;


--S1_grant_0 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|grant_0
--operation mode is normal

S1_grant_0_lut_out = !S1_grant_0;
S1_grant_0 = DFFEA(S1_grant_0_lut_out, clk, B1_d2_reset_n, , S1L3, , );


--S1L8 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[3]~252
--operation mode is normal

S1L8 = S1L99 & (S1L11 # S1L13 # S1L01);


--S1L2 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|add~57
--operation mode is normal

S1L2 = !S1_cfi_flash_0_s1_wait_counter[1] & !S1_cfi_flash_0_s1_wait_counter[0];


--E1L341 is UP3_Board:inst|cpu_0_data_master_arbitrator:the_cpu_0_data_master|r_1~73
--operation mode is normal

E1L341 = !S1_cfi_flash_0_s1_wait_counter[3] & !S1_cfi_flash_0_s1_wait_counter[2] & !S1_cfi_flash_0_s1_wait_counter[1];


--S1L5 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[0]~253
--operation mode is normal

S1L5 = !S1_cfi_flash_0_s1_wait_counter[0] & (S1_cfi_flash_0_s1_wait_counter[3] # S1_cfi_flash_0_s1_wait_counter[2] # S1_cfi_flash_0_s1_wait_counter[1]);


--S1L6 is UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|cfi_flash_0_s1_counter_load_value[2]~255
--operation mode is normal

S1L6 = S1_cfi_flash_0_s1_wait_counter[2] & (S1_cfi_flash_0_s1_wait_counter[1] # S1_cfi_flash_0_s1_wait_counter[0]) # !S1_cfi_flash_0_s1_wait_counter[2] & !S1_cfi_flash_0_s1_wait_counter[1] & !S1_cfi_flash_0_s1_wait_counter[0] & S1_cfi_flash_0_s1_wait_counter[3];


--B1_d1_reset_n_sources is UP3_Board:inst|d1_reset_n_sources
--operation mode is normal

B1_d1_reset_n_sources_lut_out = reset_n;
B1_d1_reset_n_sources = DFFEA(B1_d1_reset_n_sources_lut_out, clk, VCC, , , , );


--Y1_result[20] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[20]
--operation mode is arithmetic

Y1_result[20] = AMPP_FUNCTION(D1_E_src2[20], D1_E_src1[20], Y1L14, D1_E_alu_sub);

--Y1L34 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[20]~COUT
--operation mode is arithmetic

Y1L34 = AMPP_FUNCTION(D1_E_src2[20], D1_E_src1[20], Y1L14, D1_E_alu_sub);


--D1_E_src1[20] is UP3_Board:inst|cpu_0:the_cpu_0|E_src1[20]
--operation mode is normal

D1_E_src1[20] = AMPP_FUNCTION(clk, AB1_q_a[20], D1_D_iw[24], D1L764, D1L963, B1_d2_reset_n, D1L863);


--D1_E_src2[20] is UP3_Board:inst|cpu_0:the_cpu_0|E_src2[20]
--operation mode is normal

D1_E_src2[20] = AMPP_FUNCTION(clk, AB1_q_b[20], D1_D_iw[21], D1_D_iw[10], D1_R_src2_use_imm, B1_d2_reset_n, D1L173, D1_R_ctrl_hi_imm);


--D1L231 is UP3_Board:inst|cpu_0:the_cpu_0|E_logic_result[20]~10528
--operation mode is normal

D1L231 = AMPP_FUNCTION(D1_R_logic_op[1], D1_E_src1[20], D1_E_src2[20], D1_R_logic_op[0]);


--D1_E_shift_rot_result[20] is UP3_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[20]
--operation mode is normal

D1_E_shift_rot_result[20] = AMPP_FUNCTION(clk, D1_E_shift_rot_result[19], D1_E_shift_rot_result[21], D1_E_src1[20], D1_R_ctrl_shift_rot_right, B1_d2_reset_n, D1_E_new_inst);


--D1L764 is UP3_Board:inst|cpu_0:the_cpu_0|add~200
--operation mode is arithmetic

D1L764 = AMPP_FUNCTION(D1_F_pc[18], D1L664);

--D1L864 is UP3_Board:inst|cpu_0:the_cpu_0|add~200COUT
--operation mode is arithmetic

D1L864 = AMPP_FUNCTION(D1_F_pc[18], D1L664);


--Y1_result[19] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[19]
--operation mode is arithmetic

Y1_result[19] = AMPP_FUNCTION(D1_E_src2[19], D1_E_src1[19], Y1L93, D1_E_alu_sub);

--Y1L14 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[19]~COUT
--operation mode is arithmetic

Y1L14 = AMPP_FUNCTION(D1_E_src2[19], D1_E_src1[19], Y1L93, D1_E_alu_sub);


--D1_E_src1[19] is UP3_Board:inst|cpu_0:the_cpu_0|E_src1[19]
--operation mode is normal

D1_E_src1[19] = AMPP_FUNCTION(clk, AB1_q_a[19], D1_D_iw[23], D1L564, D1L963, B1_d2_reset_n, D1L863);


--D1_E_src2[19] is UP3_Board:inst|cpu_0:the_cpu_0|E_src2[19]
--operation mode is normal

D1_E_src2[19] = AMPP_FUNCTION(clk, AB1_q_b[19], D1_D_iw[21], D1_D_iw[9], D1_R_src2_use_imm, B1_d2_reset_n, D1L173, D1_R_ctrl_hi_imm);


--D1L131 is UP3_Board:inst|cpu_0:the_cpu_0|E_logic_result[19]~10529
--operation mode is normal

D1L131 = AMPP_FUNCTION(D1_R_logic_op[1], D1_E_src1[19], D1_E_src2[19], D1_R_logic_op[0]);


--D1_E_shift_rot_result[19] is UP3_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[19]
--operation mode is normal

D1_E_shift_rot_result[19] = AMPP_FUNCTION(clk, D1_E_shift_rot_result[18], D1_E_shift_rot_result[20], D1_E_src1[19], D1_R_ctrl_shift_rot_right, B1_d2_reset_n, D1_E_new_inst);


--D1L564 is UP3_Board:inst|cpu_0:the_cpu_0|add~199
--operation mode is arithmetic

D1L564 = AMPP_FUNCTION(D1_F_pc[17], D1L464);

--D1L664 is UP3_Board:inst|cpu_0:the_cpu_0|add~199COUT
--operation mode is arithmetic

D1L664 = AMPP_FUNCTION(D1_F_pc[17], D1L464);


--Y1_result[18] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[18]
--operation mode is arithmetic

Y1_result[18] = AMPP_FUNCTION(D1_E_src2[18], D1_E_src1[18], Y1L73, D1_E_alu_sub);

--Y1L93 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[18]~COUT
--operation mode is arithmetic

Y1L93 = AMPP_FUNCTION(D1_E_src2[18], D1_E_src1[18], Y1L73, D1_E_alu_sub);


--D1_E_src1[18] is UP3_Board:inst|cpu_0:the_cpu_0|E_src1[18]
--operation mode is normal

D1_E_src1[18] = AMPP_FUNCTION(clk, AB1_q_a[18], D1_D_iw[22], D1L364, D1L963, B1_d2_reset_n, D1L863);


--D1_E_src2[18] is UP3_Board:inst|cpu_0:the_cpu_0|E_src2[18]
--operation mode is normal

D1_E_src2[18] = AMPP_FUNCTION(clk, AB1_q_b[18], D1_D_iw[21], D1_D_iw[8], D1_R_src2_use_imm, B1_d2_reset_n, D1L173, D1_R_ctrl_hi_imm);


--D1L031 is UP3_Board:inst|cpu_0:the_cpu_0|E_logic_result[18]~10530
--operation mode is normal

D1L031 = AMPP_FUNCTION(D1_R_logic_op[1], D1_E_src1[18], D1_E_src2[18], D1_R_logic_op[0]);


--D1_E_shift_rot_result[18] is UP3_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[18]
--operation mode is normal

D1_E_shift_rot_result[18] = AMPP_FUNCTION(clk, D1_E_shift_rot_result[17], D1_E_shift_rot_result[19], D1_E_src1[18], D1_R_ctrl_shift_rot_right, B1_d2_reset_n, D1_E_new_inst);


--D1L364 is UP3_Board:inst|cpu_0:the_cpu_0|add~198
--operation mode is arithmetic

D1L364 = AMPP_FUNCTION(D1_F_pc[16], D1L264);

--D1L464 is UP3_Board:inst|cpu_0:the_cpu_0|add~198COUT
--operation mode is arithmetic

D1L464 = AMPP_FUNCTION(D1_F_pc[16], D1L264);


--Y1_result[17] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[17]
--operation mode is arithmetic

Y1_result[17] = AMPP_FUNCTION(D1_E_src2[17], D1_E_src1[17], Y1L53, D1_E_alu_sub);

--Y1L73 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[17]~COUT
--operation mode is arithmetic

Y1L73 = AMPP_FUNCTION(D1_E_src2[17], D1_E_src1[17], Y1L53, D1_E_alu_sub);


--D1_E_src1[17] is UP3_Board:inst|cpu_0:the_cpu_0|E_src1[17]
--operation mode is normal

D1_E_src1[17] = AMPP_FUNCTION(clk, AB1_q_a[17], D1_D_iw[21], D1L164, D1L963, B1_d2_reset_n, D1L863);


--D1_E_src2[17] is UP3_Board:inst|cpu_0:the_cpu_0|E_src2[17]
--operation mode is normal

D1_E_src2[17] = AMPP_FUNCTION(clk, AB1_q_b[17], D1_D_iw[21], D1_D_iw[7], D1_R_src2_use_imm, B1_d2_reset_n, D1L173, D1_R_ctrl_hi_imm);


--D1L921 is UP3_Board:inst|cpu_0:the_cpu_0|E_logic_result[17]~10531
--operation mode is normal

D1L921 = AMPP_FUNCTION(D1_R_logic_op[1], D1_E_src1[17], D1_E_src2[17], D1_R_logic_op[0]);


--D1_E_shift_rot_result[17] is UP3_Board:inst|cpu_0:the_cpu_0|E_shift_rot_result[17]
--operation mode is normal

D1_E_shift_rot_result[17] = AMPP_FUNCTION(clk, D1_E_shift_rot_result[16], D1_E_shift_rot_result[18], D1_E_src1[17], D1_R_ctrl_shift_rot_right, B1_d2_reset_n, D1_E_new_inst);


--D1L164 is UP3_Board:inst|cpu_0:the_cpu_0|add~197
--operation mode is arithmetic

D1L164 = AMPP_FUNCTION(D1_F_pc[15], D1L064);

--D1L264 is UP3_Board:inst|cpu_0:the_cpu_0|add~197COUT
--operation mode is arithmetic

D1L264 = AMPP_FUNCTION(D1_F_pc[15], D1L064);


--Y1_result[16] is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|result[16]
--operation mode is arithmetic

Y1_result[16] = AMPP_FUNCTION(D1_E_src2[16], D1_E_src1[16], Y1L33, D1_E_alu_sub);

--Y1L53 is UP3_Board:inst|cpu_0:the_cpu_0|lpm_add_sub:add_rtl_1|alt_stratix_add_sub:stratix_adder|add_sub_cell[16]~COUT
--operation mode is arithmetic

Y1L53 = AMPP_FUNCTION(D1_E_src2[16], D1_E_src1[16], Y1L33, D1_E_alu_sub);


--D1_E_src1[16] is UP3_Board:inst|cpu_0:the_cpu_0|E_src1[16]
--operation mode is normal

D1_E_src1[16] = AMPP_FUNCTION(clk, AB1_q_a[16], D1_D_iw[20], D1L954, D1L963, B1_d2_reset_n, D1L863);


--D1_E_src2[16] is UP3_Board:inst|cpu_0:the_cpu_0|E_src2[16]
--operation mode is normal

D1_E_src2[16] = AMPP_FUNCTION(clk, AB1_q_b[16], D1_D_iw[21], D1_D_iw[6], D1_R_src2_use_imm, B1_d2_reset_n, D1L173, D1_R_ctrl_hi_imm);


--D1L821 is UP3_Board:inst|cpu_0:the_cpu_0|E_logic_result[16]~10532
--operation mode is normal

D1L821 = AMPP_FUNCTION(D1_R_logic_op[1], D1_E_src1[16], D1_E_src2[16], D1_R_logic_op[0]);


--D1_E_shift_rot_result[16] is UP3_Board: