📄 up3_board.tan.rpt
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+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; altera_internal_jtag~TCKUTAP ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 101.79 MHz ( period = 9.824 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[29] ; clk ; clk ; None ; None ; None ;
; N/A ; 101.79 MHz ( period = 9.824 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[13] ; clk ; clk ; None ; None ; None ;
; N/A ; 101.80 MHz ( period = 9.823 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[18] ; clk ; clk ; None ; None ; None ;
; N/A ; 101.80 MHz ( period = 9.823 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[22] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.18 MHz ( period = 9.787 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[25] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.41 MHz ( period = 9.765 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|F_pc[19] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[29] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.41 MHz ( period = 9.765 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|F_pc[19] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[13] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.42 MHz ( period = 9.764 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|F_pc[19] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[18] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.42 MHz ( period = 9.764 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|F_pc[19] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[22] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.66 MHz ( period = 9.741 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|cpu_0_test_bench:the_cpu_0_test_bench|d_write ; UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn ; clk ; clk ; None ; None ; None ;
; N/A ; 102.80 MHz ( period = 9.728 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|F_pc[19] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[25] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.85 MHz ( period = 9.723 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[20] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[29] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.85 MHz ( period = 9.723 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[20] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[13] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.86 MHz ( period = 9.722 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[20] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[18] ; clk ; clk ; None ; None ; None ;
; N/A ; 102.86 MHz ( period = 9.722 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[20] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[22] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.24 MHz ( period = 9.686 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[20] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[25] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.49 MHz ( period = 9.663 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[30] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.53 MHz ( period = 9.659 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|d_byteenable[1] ; UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|tri_state_bridge_0_readn ; clk ; clk ; None ; None ; None ;
; N/A ; 103.62 MHz ( period = 9.651 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[13] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[29] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.62 MHz ( period = 9.651 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[13] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[13] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.63 MHz ( period = 9.650 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[13] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[18] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.63 MHz ( period = 9.650 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[13] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[22] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.82 MHz ( period = 9.632 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[11] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[29] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.82 MHz ( period = 9.632 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[11] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[13] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.83 MHz ( period = 9.631 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[11] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[18] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.83 MHz ( period = 9.631 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[11] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[22] ; clk ; clk ; None ; None ; None ;
; N/A ; 103.94 MHz ( period = 9.621 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[15] ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[29] ; clk ; clk ; None ; None ; None ;
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