up3_board.tan.rpt

NIOSII 实验指导

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+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                               ;
+-------------------------------------------------------+--------------------+------+----+
; Option                                                ; Setting            ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name                                           ; EP1C6Q240C8        ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                     ; To                                                                                                  ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.644 ns                         ; reset_n                                                                                                                  ; UP3_Board:inst|d1_reset_n_sources                                                                   ;                              ; clk                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 7.675 ns                         ; UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|d1_in_a_write_cycle        ; ext_data[15]                                                                                        ; clk                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                 ; altera_reserved_tdo                                                                                 ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.971 ns                         ; altera_internal_jtag                                                                                                     ; UP3_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|wdata[7] ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 5.093 ns                         ; UP3_Board:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave|write_n_to_the_cfi_flash_0 ; we_n                                                                                                ; clk                          ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                 ; altera_reserved_tdo                                                                                 ;                              ;                              ; 0            ;
; Clock Setup: 'clk'                          ; N/A   ; None          ; 101.79 MHz ( period = 9.824 ns ) ; UP3_Board:inst|cpu_0:the_cpu_0|W_alu_result[14]                                                                          ; UP3_Board:inst|cpu_0:the_cpu_0|D_iw[13]                                                             ; clk                          ; clk                          ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 137.29 MHz ( period = 7.284 ns ) ; sld_hub:sld_hub_inst|jtag_debug_mode_usr1                                                                                ; UP3_Board:inst|jtag_uart_0:the_jtag_uart_0|alt_jtag_atlantic:jtag_uart_0_alt_jtag_atlantic|jupdate  ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                          ;                                                                                                     ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+