up3_board_log.txt

NIOSII 实验指导

Altera SOPC Builder Version 4.01 Build 214
Copyright (c) 1999-2004 Altera Corporation.  All rights reserved.


# 2004.09.12 15:33:45 (*) mk_custom_sdk starting
# 2004.09.12 15:33:45 (*) Reading project C:/altera_trn/board/UP3_Board/system/UP3_Board.ptf.

# 2004.09.12 15:33:46 (*) Finding all CPUs

# 2004.09.12 15:33:46 (*) Finding all available components

# 2004.09.12 15:33:46 (*) Found 40 components

# 2004.09.12 15:33:48 (*) Finding all peripherals

# 2004.09.12 15:33:48 (*) Finding software components

# 2004.09.12 15:33:49 (*) (All SDK Generation Skipped)
# 2004.09.12 15:33:49 (*) (All TCL Script Generation Skipped)
# 2004.09.12 15:33:49 (*) (No Libraries Built)
# 2004.09.12 15:33:49 (*) (Contents Generation Skipped)
# 2004.09.12 15:33:49 (*) mk_custom_sdk finishing

# 2004.09.12 15:33:49 (*) Starting generation for system: UP3_Board.

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# 2004.09.12 15:33:55 (*) Running Generator Program for cpu_0

Redirecting generation messages for cpu_0 to file cpu_0_gen_log_0.txt

# 2004.09.12 15:34:26 (*) Running Generator Program for firmware_ROM

# 2004.09.12 15:34:30 (*) Running Generator Program for data_RAM

# 2004.09.12 15:34:34 (*) Running Generator Program for payload_buffer

# 2004.09.12 15:34:38 (*) Running Generator Program for jtag_uart_0

# 2004.09.12 15:34:47 (*) Running Generator Program for sysid

# 2004.09.12 15:34:52 (*) Running Generator Program for Board_System

# 2004.09.12 15:34:54 (*) Now generating custom board component and flash programmer design.
# 2004.09.12 15:34:54 (*) After generation is complete, you must do the following next steps:
# 2004.09.12 15:34:54 (*)  1.) Update the system symbol in QuartusII
# 2004.09.12 15:34:54 (*)  2.) Add flash pins to the .bdf schematic file and connect them to the flash
# 2004.09.12 15:34:54 (*)       ports on the updated symbol.

# 2004.09.12 15:34:54 (*)  3.) Add pins to the .bdf schematic file to dissable any other external devices
# 2004.09.12 15:34:54 (*)       that are on the same tri-state bus as flash.
# 2004.09.12 15:34:54 (*)   4.) Assign the schematic pins you added to the associated device pins that
# 2004.09.12 15:34:54 (*)       connect to the external devices
# 2004.09.12 15:34:54 (*)  5.) Compile the design in QuartusII.

# 2004.09.12 15:34:54 (*) It is important that you consult the document "NiosII Flash Programmer User Guide",
# 2004.09.12 15:34:54 (*)  available at www.altera.com, before attempting to port the NiosII Flash Programmer
# 2004.09.12 15:34:54 (*)  to custom boards.


# 2004.09.12 15:34:55 (*) Running Generator Program for cfi_flash_0


# 2004.09.12 15:34:58 (*) Making arbitration and system (top) modules.

# 2004.09.12 15:35:20 (*) Symbol C:/altera_trn/board/UP3_Board/system/UP3_Board.bsf already exists, no need to regenerate
# 2004.09.12 15:35:20 (*) Creating command-line system-generation script: C:/altera_trn/board/UP3_Board/system/UP3_Board_generation_script

# 2004.09.12 15:35:20 (*) Setting up Quartus with UP3_Board_setup_quartus_native_synthesis.tcl
c:/altera/quartus40/bin/quartus_cmd -f UP3_Board_setup_quartus_native_synthesis.tcl


Info: Processing of Quartus II Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Full Version started at time 09/12/2004 15:35:22

# 2004.09.12 15:35:23 (*) Completed generation for system: UP3_Board.
# 2004.09.12 15:35:23 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : C:/altera_trn/board/UP3_Board/system/UP3_Board.ptf 
  System HDL Model : C:/altera_trn/board/UP3_Board/system/UP3_Board.v 
  System Generation Script : C:/altera_trn/board/UP3_Board/system/UP3_Board_generation_script 
  cpu_0 include files such as memory maps : C:/altera_trn/board/UP3_Board/system/cpu_0_sdk/inc/ 
  cpu_0 library files : C:/altera_trn/board/UP3_Board/system/cpu_0_sdk/lib/ 
  cpu_0 example programs : C:/altera_trn/board/UP3_Board/system/cpu_0_sdk/src/ 


# 2004.09.12 15:35:23 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


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