cpu_0_test_bench.v

NIOSII 实验指导

  assign D_op_rsv42 = D_iw_op[5 : 0] == 42;
  assign D_op_rsv26 = D_iw_op[5 : 0] == 26;
  assign D_op_rsv27 = D_iw_op[5 : 0] == 27;
  assign D_op_andhi = D_iw_op[5 : 0] == 44;
  assign D_op_rsv61 = D_iw_op[5 : 0] == 61;
  assign D_op_rsv29 = D_iw_op[5 : 0] == 29;
  assign D_op_sth = D_iw_op[5 : 0] == 13;
  assign D_op_rsv62 = D_iw_op[5 : 0] == 62;
  assign D_op_rsv63 = D_iw_op[5 : 0] == 63;
  assign D_op_flushd = D_iw_op[5 : 0] == 59;
  assign D_op_ldhio = D_iw_op[5 : 0] == 47;
  assign D_op_rsv49 = D_iw_op[5 : 0] == 49;
  assign D_op_orhi = D_iw_op[5 : 0] == 52;
  assign D_op_call = D_iw_op[5 : 0] == 0;
  assign D_op_cmpeqi = D_iw_op[5 : 0] == 32;
  assign D_op_ldwio = D_iw_op[5 : 0] == 55;
  assign D_op_custom = D_iw_op[5 : 0] == 50;
  assign D_op_stw = D_iw_op[5 : 0] == 21;
  assign D_op_ldbu = D_iw_op[5 : 0] == 3;
  assign D_op_stbio = D_iw_op[5 : 0] == 37;
  assign D_op_rsv10 = D_iw_op[5 : 0] == 10;
  assign D_op_cmpgeui = D_iw_op[5 : 0] == 40;
  assign D_op_xori = D_iw_op[5 : 0] == 28;
  assign D_op_rsv31 = D_iw_op[5 : 0] == 31;
  assign D_op_addi = D_iw_op[5 : 0] == 4;
  assign D_op_ldhu = D_iw_op[5 : 0] == 11;
  assign D_op_rsv33 = D_iw_op[5 : 0] == 33;
  assign D_op_rsv17 = D_iw_op[5 : 0] == 17;
  assign D_op_rsv34 = D_iw_op[5 : 0] == 34;
  assign D_op_bne = D_iw_op[5 : 0] == 30;
  assign D_op_rsv18 = D_iw_op[5 : 0] == 18;
  assign D_op_rsv19 = D_iw_op[5 : 0] == 19;
  assign D_op_xorhi = D_iw_op[5 : 0] == 60;
  assign D_op_rsv56 = D_iw_op[5 : 0] == 56;
  assign D_op_bltu = D_iw_op[5 : 0] == 54;
  assign D_op_rsv57 = D_iw_op[5 : 0] == 57;
  assign D_op_ldbuio = D_iw_op[5 : 0] == 35;
  assign D_op_ldb = D_iw_op[5 : 0] == 7;
  assign D_op_sthio = D_iw_op[5 : 0] == 45;
  assign D_op_initd = D_iw_op[5 : 0] == 51;
  assign D_op_blt = D_iw_op[5 : 0] == 22;
  assign D_op_cmplti = D_iw_op[5 : 0] == 16;
  assign D_op_br = D_iw_op[5 : 0] == 6;
  assign D_op_ldh = D_iw_op[5 : 0] == 15;
  assign D_op_initi = D_op_opx & (D_iw_opx[5 : 0] == 41);
  assign D_op_roli = D_op_opx & (D_iw_opx[5 : 0] == 2);
  assign D_op_cmpne = D_op_opx & (D_iw_opx[5 : 0] == 24);
  assign D_op_nor = D_op_opx & (D_iw_opx[5 : 0] == 6);
  assign D_op_trap = D_op_opx & (D_iw_opx[5 : 0] == 45);
  assign D_op_sll = D_op_opx & (D_iw_opx[5 : 0] == 19);
  assign D_op_sra = D_op_opx & (D_iw_opx[5 : 0] == 59);
  assign D_op_cmpltu = D_op_opx & (D_iw_opx[5 : 0] == 48);
  assign D_op_wrctl = D_op_opx & (D_iw_opx[5 : 0] == 46);
  assign D_op_bret = D_op_opx & (D_iw_opx[5 : 0] == 9);
  assign D_op_rol = D_op_opx & (D_iw_opx[5 : 0] == 3);
  assign D_op_and = D_op_opx & (D_iw_opx[5 : 0] == 14);
  assign D_op_rsvx00 = D_op_opx & (D_iw_opx[5 : 0] == 0);
  assign D_op_rsvx20 = D_op_opx & (D_iw_opx[5 : 0] == 20);
  assign D_op_cmplt = D_op_opx & (D_iw_opx[5 : 0] == 16);
  assign D_op_ror = D_op_opx & (D_iw_opx[5 : 0] == 11);
  assign D_op_hbreak = D_op_opx & (D_iw_opx[5 : 0] == 53);
  assign D_op_callr = D_op_opx & (D_iw_opx[5 : 0] == 29);
  assign D_op_rsvx21 = D_op_opx & (D_iw_opx[5 : 0] == 21);
  assign D_op_srl = D_op_opx & (D_iw_opx[5 : 0] == 27);
  assign D_op_intr = D_op_opx & (D_iw_opx[5 : 0] == 61);
  assign D_op_rsvx25 = D_op_opx & (D_iw_opx[5 : 0] == 25);
  assign D_op_eret = D_op_opx & (D_iw_opx[5 : 0] == 1);
  assign D_op_rsvx42 = D_op_opx & (D_iw_opx[5 : 0] == 42);
  assign D_op_cmpge = D_op_opx & (D_iw_opx[5 : 0] == 8);
  assign D_op_rsvx43 = D_op_opx & (D_iw_opx[5 : 0] == 43);
  assign D_op_rsvx60 = D_op_opx & (D_iw_opx[5 : 0] == 60);
  assign D_op_rsvx44 = D_op_opx & (D_iw_opx[5 : 0] == 44);
  assign D_op_divu = D_op_opx & (D_iw_opx[5 : 0] == 36);
  assign D_op_rsvx62 = D_op_opx & (D_iw_opx[5 : 0] == 62);
  assign D_op_flushi = D_op_opx & (D_iw_opx[5 : 0] == 12);
  assign D_op_rsvx63 = D_op_opx & (D_iw_opx[5 : 0] == 63);
  assign D_op_rsvx47 = D_op_opx & (D_iw_opx[5 : 0] == 47);
  assign D_op_cmpgeu = D_op_opx & (D_iw_opx[5 : 0] == 40);
  assign D_op_mulxss = D_op_opx & (D_iw_opx[5 : 0] == 31);
  assign D_op_break = D_op_opx & (D_iw_opx[5 : 0] == 52);
  assign D_op_div = D_op_opx & (D_iw_opx[5 : 0] == 37);
  assign D_op_cmpeq = D_op_opx & (D_iw_opx[5 : 0] == 32);
  assign D_op_slli = D_op_opx & (D_iw_opx[5 : 0] == 18);
  assign D_op_mulxsu = D_op_opx & (D_iw_opx[5 : 0] == 23);
  assign D_op_nextpc = D_op_opx & (D_iw_opx[5 : 0] == 28);
  assign D_op_flushp = D_op_opx & (D_iw_opx[5 : 0] == 4);
  assign D_op_xor = D_op_opx & (D_iw_opx[5 : 0] == 30);
  assign D_op_sync = D_op_opx & (D_iw_opx[5 : 0] == 54);
  assign D_op_mulxuu = D_op_opx & (D_iw_opx[5 : 0] == 7);
  assign D_op_mul = D_op_opx & (D_iw_opx[5 : 0] == 39);
  assign D_op_rsvx10 = D_op_opx & (D_iw_opx[5 : 0] == 10);
  assign D_op_sub = D_op_opx & (D_iw_opx[5 : 0] == 57);
  assign D_op_srli = D_op_opx & (D_iw_opx[5 : 0] == 26);
  assign D_op_jmp = D_op_opx & (D_iw_opx[5 : 0] == 13);
  assign D_op_rsvx15 = D_op_opx & (D_iw_opx[5 : 0] == 15);
  assign D_op_rsvx33 = D_op_opx & (D_iw_opx[5 : 0] == 33);
  assign D_op_rsvx17 = D_op_opx & (D_iw_opx[5 : 0] == 17);
  assign D_op_rsvx50 = D_op_opx & (D_iw_opx[5 : 0] == 50);
  assign D_op_rsvx34 = D_op_opx & (D_iw_opx[5 : 0] == 34);
  assign D_op_rsvx51 = D_op_opx & (D_iw_opx[5 : 0] == 51);
  assign D_op_rdctl = D_op_opx & (D_iw_opx[5 : 0] == 38);
  assign D_op_rsvx35 = D_op_opx & (D_iw_opx[5 : 0] == 35);
  assign D_op_or = D_op_opx & (D_iw_opx[5 : 0] == 22);
  assign D_op_add = D_op_opx & (D_iw_opx[5 : 0] == 49);
  assign D_op_srai = D_op_opx & (D_iw_opx[5 : 0] == 58);
  assign D_op_rsvx55 = D_op_opx & (D_iw_opx[5 : 0] == 55);
  assign D_op_rsvx56 = D_op_opx & (D_iw_opx[5 : 0] == 56);
  assign D_op_ret = D_op_opx & (D_iw_opx[5 : 0] == 5);

//exemplar translate_off
`ifdef MODEL_TECH
//////////////// SIMULATION-ONLY CONTENTS
  //Clearing 'X' data bits
  assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;

  assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
  assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
  assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
  assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
  assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
  assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
  assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
  assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
  assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
  assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
  assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
  assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
  assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
  assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
  assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
  assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
  assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
  assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
  assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
  assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
  assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
  assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
  assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
  assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
  assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
  assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
  assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
  assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
  assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
  assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
  assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
  assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
  assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
  assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
  assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
  assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
  assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
  assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
  assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
  assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
  assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
  assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
  assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
  assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
  assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
  assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
  assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
  assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
  assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
  assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
  assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
  assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
  assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
  assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
  assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
  assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
  assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
  assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
  assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
  assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
  assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
  assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
  assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
  always @(posedge clk)
    begin
      if (reset_n)
          if (^(F_valid) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/F_valid is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk)
    begin
      if (reset_n)
          if (^(D_valid) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/D_valid is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk)
    begin
      if (reset_n)
          if (^(E_valid) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/E_valid is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk)
    begin
      if (reset_n)
          if (^(W_valid) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/W_valid is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (W_valid)
          if (^(R_wr_dst_reg) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/R_wr_dst_reg is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (W_valid & R_wr_dst_reg)
          if (^(W_wr_data) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/W_wr_data is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (W_valid & R_wr_dst_reg)
          if (^(R_dst_regnum) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/R_dst_regnum is 'x'\n", $time);
              $stop;
            end
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
        begin
        end
      else if (W_valid & R_ctrl_ld)
          if (^(R_dst_regnum) === 1'bx)
            begin
              $write("%0d ns: ERROR: cpu_0_test_bench/R_dst_regnum is 'x'\n", $time);
              $stop;
            end
    end