up3_board.v

NIOSII 实验指导

          cpu_0_instruction_master_dbs_address <= next_dbs_address;
    end


  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = cpu_0_instruction_master_read_data_valid_payload_buffer_s1 |
    cpu_0_instruction_master_read_data_valid_cfi_flash_0_s1;


  // exemplar attribute cpu_0_instruction_master_arbitrator auto_dissolve FALSE

endmodule


module data_RAM_s1_arbitrator (
                                // inputs:
                                 clk,
                                 cpu_0_data_master_address_to_slave,
                                 cpu_0_data_master_byteenable,
                                 cpu_0_data_master_read,
                                 cpu_0_data_master_waitrequest,
                                 cpu_0_data_master_write,
                                 cpu_0_data_master_writedata,
                                 cpu_0_instruction_master_address_to_slave,
                                 cpu_0_instruction_master_read,
                                 d2_reset_n,
                                 data_RAM_s1_readdata,

                                // outputs:
                                 cpu_0_data_master_granted_data_RAM_s1,
                                 cpu_0_data_master_qualified_request_data_RAM_s1,
                                 cpu_0_data_master_read_data_valid_data_RAM_s1,
                                 cpu_0_data_master_requests_data_RAM_s1,
                                 cpu_0_data_master_s_turn_at_data_RAM_s1,
                                 cpu_0_instruction_master_granted_data_RAM_s1,
                                 cpu_0_instruction_master_qualified_request_data_RAM_s1,
                                 cpu_0_instruction_master_read_data_valid_data_RAM_s1,
                                 cpu_0_instruction_master_requests_data_RAM_s1,
                                 d1_cpu_0_data_master_granted_data_RAM_s1,
                                 d1_cpu_0_instruction_master_granted_data_RAM_s1,
                                 d1_data_RAM_s1_end_xfer,
                                 data_RAM_s1_address,
                                 data_RAM_s1_byteenable,
                                 data_RAM_s1_chipselect,
                                 data_RAM_s1_readdata_from_sa,
                                 data_RAM_s1_write,
                                 data_RAM_s1_writedata,
                                 registered_cpu_0_data_master_read_data_valid_data_RAM_s1
                              );

  output           cpu_0_data_master_granted_data_RAM_s1;
  output           cpu_0_data_master_qualified_request_data_RAM_s1;
  output           cpu_0_data_master_read_data_valid_data_RAM_s1;
  output           cpu_0_data_master_requests_data_RAM_s1;
  output           cpu_0_data_master_s_turn_at_data_RAM_s1;
  output           cpu_0_instruction_master_granted_data_RAM_s1;
  output           cpu_0_instruction_master_qualified_request_data_RAM_s1;
  output           cpu_0_instruction_master_read_data_valid_data_RAM_s1;
  output           cpu_0_instruction_master_requests_data_RAM_s1;
  output           d1_cpu_0_data_master_granted_data_RAM_s1;
  output           d1_cpu_0_instruction_master_granted_data_RAM_s1;
  output           d1_data_RAM_s1_end_xfer;
  output  [  7: 0] data_RAM_s1_address;
  output  [  3: 0] data_RAM_s1_byteenable;
  output           data_RAM_s1_chipselect;
  output  [ 31: 0] data_RAM_s1_readdata_from_sa;
  output           data_RAM_s1_write;
  output  [ 31: 0] data_RAM_s1_writedata;
  output           registered_cpu_0_data_master_read_data_valid_data_RAM_s1;
  input            clk;
  input   [ 21: 0] cpu_0_data_master_address_to_slave;
  input   [  3: 0] cpu_0_data_master_byteenable;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_waitrequest;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input   [ 21: 0] cpu_0_instruction_master_address_to_slave;
  input            cpu_0_instruction_master_read;
  input            d2_reset_n;
  input   [ 31: 0] data_RAM_s1_readdata;

  wire             cpu_0_data_master_granted_data_RAM_s1;
  wire             cpu_0_data_master_qualified_request_data_RAM_s1;
  wire             cpu_0_data_master_read_data_valid_data_RAM_s1;
  reg              cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
  wire             cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in;
  wire             cpu_0_data_master_requests_data_RAM_s1;
  reg              cpu_0_data_master_s_turn_at_data_RAM_s1;
  wire             cpu_0_instruction_master_granted_data_RAM_s1;
  wire             cpu_0_instruction_master_qualified_request_data_RAM_s1;
  wire             cpu_0_instruction_master_read_data_valid_data_RAM_s1;
  reg              cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register;
  wire             cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_in;
  wire             cpu_0_instruction_master_requests_data_RAM_s1;
  reg              d1_cpu_0_data_master_granted_data_RAM_s1;
  reg              d1_cpu_0_instruction_master_granted_data_RAM_s1;
  reg              d1_data_RAM_s1_end_xfer;
  wire    [  7: 0] data_RAM_s1_address;
  wire    [  3: 0] data_RAM_s1_byteenable;
  wire             data_RAM_s1_chipselect;
  wire             data_RAM_s1_end_xfer;
  wire             data_RAM_s1_in_a_read_cycle;
  wire             data_RAM_s1_in_a_write_cycle;
  wire    [ 31: 0] data_RAM_s1_readdata_from_sa;
  wire             data_RAM_s1_waits_for_read;
  wire             data_RAM_s1_waits_for_write;
  wire             data_RAM_s1_write;
  wire    [ 31: 0] data_RAM_s1_writedata;
  reg              grant_0;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             next_grant_0;
  wire             p1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
  wire             p1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register;
  wire             registered_cpu_0_data_master_read_data_valid_data_RAM_s1;
  wire             wait_for_data_RAM_s1_counter;
  //cpu_0_data_master_granted_data_RAM_s1 granted, which is an e_assign
  assign cpu_0_data_master_granted_data_RAM_s1 = cpu_0_data_master_qualified_request_data_RAM_s1 &
    (!cpu_0_instruction_master_qualified_request_data_RAM_s1 |
    (
    ((d1_data_RAM_s1_end_xfer)?
    cpu_0_data_master_s_turn_at_data_RAM_s1 : d1_cpu_0_data_master_granted_data_RAM_s1
    )
    )
    );

  //cpu_0_instruction_master_granted_data_RAM_s1 granted, which is an e_assign
  assign cpu_0_instruction_master_granted_data_RAM_s1 = cpu_0_instruction_master_qualified_request_data_RAM_s1 &
    (!cpu_0_data_master_qualified_request_data_RAM_s1 |
    (
    ((d1_data_RAM_s1_end_xfer)?
    (!cpu_0_data_master_s_turn_at_data_RAM_s1) : d1_cpu_0_instruction_master_granted_data_RAM_s1
    )
    )
    );

  assign cpu_0_data_master_requests_data_RAM_s1 = ({cpu_0_data_master_address_to_slave[21 : 10] , 10'b0} == 22'h10000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign data_RAM_s1_readdata_from_sa = data_RAM_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign data_RAM_s1_readdata_from_sa = data_RAM_s1_readdata;

  //registered rdv signal_name registered_cpu_0_data_master_read_data_valid_data_RAM_s1 assignment, which is an e_assign
  assign registered_cpu_0_data_master_read_data_valid_data_RAM_s1 = cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in;

  assign cpu_0_data_master_qualified_request_data_RAM_s1 = cpu_0_data_master_requests_data_RAM_s1 & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
  assign cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in = cpu_0_data_master_granted_data_RAM_s1 & cpu_0_data_master_read & ~data_RAM_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register);
  assign p1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register = {cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register, cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register_in};
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register <= 0;
      else if (1)
          cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
    end


  assign cpu_0_data_master_read_data_valid_data_RAM_s1 = cpu_0_data_master_read_data_valid_data_RAM_s1_shift_register;
  //data_RAM_s1_writedata mux, which is an e_mux
  assign data_RAM_s1_writedata = cpu_0_data_master_writedata;

  assign cpu_0_instruction_master_requests_data_RAM_s1 = ({cpu_0_instruction_master_address_to_slave[21 : 10] , 10'b0} == 22'h10000) & (cpu_0_instruction_master_read);
  assign cpu_0_instruction_master_qualified_request_data_RAM_s1 = cpu_0_instruction_master_requests_data_RAM_s1 & ~((cpu_0_instruction_master_read & ((|cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register))));
  assign cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_in = cpu_0_instruction_master_granted_data_RAM_s1 & cpu_0_instruction_master_read & ~data_RAM_s1_waits_for_read & ~(|cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register);
  assign p1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register = {cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register, cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register_in};
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register <= 0;
      else if (1)
          cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register;
    end


  assign cpu_0_instruction_master_read_data_valid_data_RAM_s1 = cpu_0_instruction_master_read_data_valid_data_RAM_s1_shift_register;
  //arbitration next grant 0 assignment, which is an e_assign
  assign next_grant_0 = (grant_0 == 1) ? 0 : (grant_0 + 1);

  //data_RAM_s1_end_xfer assignment, which is an e_assign
  assign data_RAM_s1_end_xfer = ~(data_RAM_s1_waits_for_read | data_RAM_s1_waits_for_write);

  //cpu_0/data_master gets granted 1
  //out of 2 times contention occurs
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          grant_0 <= 0;
      else if (data_RAM_s1_end_xfer & (cpu_0_data_master_qualified_request_data_RAM_s1) & 
((cpu_0_instruction_master_qualified_request_data_RAM_s1)
))
          grant_0 <= next_grant_0;
    end


  //cpu_0/data_master wins data_RAM/s1 at begin_xfer, which is an e_register
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          cpu_0_data_master_s_turn_at_data_RAM_s1 <= 0;
      else if (1)
          cpu_0_data_master_s_turn_at_data_RAM_s1 <= grant_0 < 1;
    end


  //d1_data_RAM_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          d1_data_RAM_s1_end_xfer <= 1;
      else if (1)
          d1_data_RAM_s1_end_xfer <= data_RAM_s1_end_xfer;
    end


  //d1_cpu_0_data_master_granted_data_RAM_s1 register granted, which is an e_register
  always @(posedge clk or negedge d2_reset_n)
    begin
      if (d2_reset_n == 0)
          d1_cpu_0_data_master_granted_data_RAM_s1 <= 0;