up3_board.qsf

NIOSII 实验指导

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		UP3_Board_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name BDF_FILE UP3_Board_top.bdf
set_global_assignment -name LAST_QUARTUS_VERSION 4.1

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_29 -to clk
set_location_assignment PIN_23 -to reset_n
set_location_assignment PIN_93 -to ext_addr\[0\]
set_location_assignment PIN_88 -to ext_addr\[1\]
set_location_assignment PIN_87 -to ext_addr\[2\]
set_location_assignment PIN_86 -to ext_addr\[3\]
set_location_assignment PIN_85 -to ext_addr\[4\]
set_location_assignment PIN_84 -to ext_addr\[5\]
set_location_assignment PIN_83 -to ext_addr\[6\]
set_location_assignment PIN_63 -to ext_addr\[7\]
set_location_assignment PIN_64 -to ext_addr\[8\]
set_location_assignment PIN_65 -to ext_addr\[9\]
set_location_assignment PIN_66 -to ext_addr\[10\]
set_location_assignment PIN_67 -to ext_addr\[11\]
set_location_assignment PIN_68 -to ext_addr\[12\]
set_location_assignment PIN_74 -to ext_addr\[13\]
set_location_assignment PIN_75 -to ext_addr\[14\]
set_location_assignment PIN_76 -to ext_addr\[15\]
set_location_assignment PIN_77 -to ext_addr\[16\]
set_location_assignment PIN_82 -to ext_addr\[17\]
set_location_assignment PIN_81 -to ext_addr\[18\]
set_location_assignment PIN_78 -to ext_addr\[19\]
set_location_assignment PIN_94 -to ext_data\[0\]
set_location_assignment PIN_96 -to ext_data\[1\]
set_location_assignment PIN_98 -to ext_data\[2\]
set_location_assignment PIN_100 -to ext_data\[3\]
set_location_assignment PIN_102 -to ext_data\[4\]
set_location_assignment PIN_104 -to ext_data\[5\]
set_location_assignment PIN_106 -to ext_data\[6\]
set_location_assignment PIN_113 -to ext_data\[7\]
set_location_assignment PIN_95 -to ext_data\[8\]
set_location_assignment PIN_97 -to ext_data\[9\]
set_location_assignment PIN_99 -to ext_data\[10\]
set_location_assignment PIN_101 -to ext_data\[11\]
set_location_assignment PIN_103 -to ext_data\[12\]
set_location_assignment PIN_105 -to ext_data\[13\]
set_location_assignment PIN_107 -to ext_data\[14\]
set_location_assignment PIN_114 -to ext_data\[15\]
set_location_assignment PIN_116 -to SRAM_ce_n
set_location_assignment PIN_118 -to oe_n
set_location_assignment PIN_79 -to we_n
set_location_assignment PIN_117 -to FLASH_ce_n
set_location_assignment PIN_119 -to SDRAM_ce_n
set_location_assignment PIN_115 -to FLASH_byte

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY UP3_Board_top

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "FAST PASSIVE PARALLEL"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS OUTPUT DRIVING AN UNSPECIFIED SIGNAL"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL