📄 smartsopc_board_cyclone_1c6.map.rpt
字号:
; a_fefifo.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/a_fefifo.tdf ;
; lpm_compare.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf ;
; comptree.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/comptree.inc ;
; comptree.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/comptree.tdf ;
; cmpchain.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/cmpchain.inc ;
; cmpchain.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf ;
; altshift.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/altshift.tdf ;
; alt_jtag_atlantic.v ; yes ; Encrypted Megafunction ; c:/altera/quartus50/libraries/megafunctions/alt_jtag_atlantic.v ;
; payload_buffer.v ; yes ; Other ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/payload_buffer.v ;
; db/altsyncram_np01.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/db/altsyncram_np01.tdf ;
; sysid.v ; yes ; Other ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/sysid.v ;
; SYS_CLK.v ; yes ; Other ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/SYS_CLK.v ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/altpll.tdf ;
; stratix_pll.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/cycloneii_pll.inc ;
; delay_reset_block.bdf ; yes ; Other ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/delay_reset_block.bdf ;
; reset_counter.v ; yes ; Other ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/reset_counter.v ;
; db/cntr_df8.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/db/cntr_df8.tdf ;
; sld_hub.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd ;
; lpm_shiftreg.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/lpm_shiftreg.tdf ;
; lpm_decode.tdf ; yes ; Megafunction ; c:/altera/quartus50/libraries/megafunctions/lpm_decode.tdf ;
; declut.inc ; yes ; Other ; c:/altera/quartus50/libraries/megafunctions/declut.inc ;
; db/decode_9ie.tdf ; yes ; Auto-Generated Megafunction ; C:/altera/kits/nios2/components/SmartSOPC_Board_Cyclone_1C6/system/db/decode_9ie.tdf ;
; sld_dffex.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd ;
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd ;
+-------------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------------------------------------------+
; Resource ; Usage ;
+-----------------------------------+---------------------------------------------+
; Total logic elements ; 3996 ;
; Total combinational functions ; 2603 ;
; -- Total 4-input functions ; 1504 ;
; -- Total 3-input functions ; 772 ;
; -- Total 2-input functions ; 251 ;
; -- Total 1-input functions ; 68 ;
; -- Total 0-input functions ; 8 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 2106 ;
; Total logic cells in carry chains ; 216 ;
; I/O pins ; 43 ;
; Total memory bits ; 59744 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; SYS_CLK:inst1|altpll:altpll_component|_clk0 ;
; Maximum fan-out ; 2180 ;
; Total fan-out ; 18224 ;
; Average fan-out ; 4.32 ;
+-----------------------------------+---------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------------------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------------------------------------------------------------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |SmartSOPC_Board_Cyclone_1C6_top ; 3996 (1) ; 2106 ; 59744 ; 43 ; 0 ; 1890 (1) ; 1393 (0) ; 713 (0) ; 216 (0) ; |SmartSOPC_Board_Cyclone_1C6_top ;
; |SYS_CLK:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |SmartSOPC_Board_Cyclone_1C6_top|SYS_CLK:inst1 ;
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |SmartSOPC_Board_Cyclone_1C6_top|SYS_CLK:inst1|altpll:altpll_component ;
; |SmartSOPC_Board_Cyclone_1C6:inst| ; 3888 (0) ; 2036 ; 59744 ; 0 ; 0 ; 1852 (0) ; 1373 (0) ; 663 (0) ; 200 (0) ; |SmartSOPC_Board_Cyclone_1C6_top|SmartSOPC_Board_Cyclone_1C6:inst ;
; |SmartSOPC_Board_Cyclone_1C6_reset_clk_domain_synch_module:SmartSOPC_Board_Cyclone_1C6_reset_clk_domain_synch| ; 2 (2) ; 2 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; |SmartSOPC_Board_Cyclone_1C6_top|SmartSOPC_Board_Cyclone_1C6:inst|SmartSOPC_Board_Cyclone_1C6_reset_clk_domain_synch_module:SmartSOPC_Board_Cyclone_1C6_reset_clk_domain_synch ;
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