smartsopc_board_cyclone_1c6.map.rpt

sopc开发板标准NIOSII模块

; Analysis & Synthesis Summary                                                   ;
+-----------------------------+--------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed May 17 16:41:21 2006            ;
; Quartus II Version          ; 5.0 Build 168 06/22/2005 SP 1.04 SJ Full Version ;
; Revision Name               ; SmartSOPC_Board_Cyclone_1C6                      ;
; Top-level Entity Name       ; SmartSOPC_Board_Cyclone_1C6_top                  ;
; Family                      ; Cyclone                                          ;
; Total logic elements        ; 3,996                                            ;
; Total pins                  ; 47                                               ;
; Total virtual pins          ; 0                                                ;
; Total memory bits           ; 59,744                                           ;
; Total PLLs                  ; 1                                                ;
+-----------------------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                                      ;
+--------------------------------------------------------------------+---------------------------------+-----------------------------+
; Option                                                             ; Setting                         ; Default Value               ;
+--------------------------------------------------------------------+---------------------------------+-----------------------------+
; Device                                                             ; EP1C6Q240C8                     ;                             ;
; Top-level entity name                                              ; SmartSOPC_Board_Cyclone_1C6_top ; SmartSOPC_Board_Cyclone_1C6 ;
; Family name                                                        ; Cyclone                         ; Stratix                     ;
; Use smart compilation                                              ; Off                             ; Off                         ;
; Restructure Multiplexers                                           ; Auto                            ; Auto                        ;
; Create Debugging Nodes for IP Cores                                ; off                             ; off                         ;
; Preserve fewer node names                                          ; On                              ; On                          ;
; Disable OpenCore Plus hardware evaluation                          ; Off                             ; Off                         ;
; Verilog Version                                                    ; Verilog_2001                    ; Verilog_2001                ;
; VHDL Version                                                       ; VHDL93                          ; VHDL93                      ;
; State Machine Processing                                           ; Auto                            ; Auto                        ;
; Extract Verilog State Machines                                     ; On                              ; On                          ;
; Extract VHDL State Machines                                        ; On                              ; On                          ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                              ; On                          ;
; NOT Gate Push-Back                                                 ; On                              ; On                          ;
; Power-Up Don't Care                                                ; On                              ; On                          ;
; Remove Redundant Logic Cells                                       ; Off                             ; Off                         ;
; Remove Duplicate Registers                                         ; On                              ; On                          ;
; Ignore CARRY Buffers                                               ; Off                             ; Off                         ;
; Ignore CASCADE Buffers                                             ; Off                             ; Off                         ;
; Ignore GLOBAL Buffers                                              ; Off                             ; Off                         ;
; Ignore ROW GLOBAL Buffers                                          ; Off                             ; Off                         ;
; Ignore LCELL Buffers                                               ; Off                             ; Off                         ;
; Ignore SOFT Buffers                                                ; On                              ; On                          ;
; Limit AHDL Integers to 32 Bits                                     ; Off                             ; Off                         ;
; Optimization Technique -- Cyclone                                  ; Balanced                        ; Balanced                    ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                              ; 70                          ;
; Auto Carry Chains                                                  ; On                              ; On                          ;
; Auto Open-Drain Pins                                               ; On                              ; On                          ;
; Remove Duplicate Logic                                             ; On                              ; On                          ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                             ; Off                         ;
; Perform gate-level register retiming                               ; Off                             ; Off                         ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                              ; On                          ;
; Auto ROM Replacement                                               ; On                              ; On                          ;
; Auto RAM Replacement                                               ; On                              ; On                          ;
; Auto Shift Register Replacement                                    ; On                              ; On                          ;
; Auto Clock Enable Replacement                                      ; On                              ; On                          ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On                              ; On                          ;
; Auto RAM Block Balancing                                           ; On                              ; On                          ;
; Auto Resource Sharing                                              ; Off                             ; Off                         ;
; Allow Any RAM Size For Recognition                                 ; Off                             ; Off                         ;
; Allow Any ROM Size For Recognition                                 ; Off                             ; Off                         ;
; Allow Any Shift Register Size For Recognition                      ; Off                             ; Off                         ;
; Maximum Number of M512 Memory Blocks                               ; -1                              ; -1                          ;