📄 smartsopc_board_cyclone_1c6.ptf
字号:
<br> 0.5-Kbyte Instruction Cache
";
}
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
}
SOFTWARE_COMPONENT altera_nios2_test
{
class = "altera_nios2_test";
class_version = "2.0";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT debug_on
{
value = "0";
comment = "Enable debug features";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "0";
}
}
SOFTWARE_COMPONENT altera_plugs_library
{
class = "altera_plugs_library";
class_version = "2.1";
WIZARD_SCRIPT_ARGUMENTS
{
CONSTANTS
{
CONSTANT PLUGS_PLUG_COUNT
{
value = "5";
comment = "Maximum number of plugs";
}
CONSTANT PLUGS_ADAPTER_COUNT
{
value = "2";
comment = "Maximum number of adapters";
}
CONSTANT PLUGS_DNS
{
value = "1";
comment = "Have routines for DNS lookups";
}
CONSTANT PLUGS_PING
{
value = "1";
comment = "Respond to icmp echo (ping) messages";
}
CONSTANT PLUGS_TCP
{
value = "1";
comment = "Support tcp in/out connections";
}
CONSTANT PLUGS_IRQ
{
value = "1";
comment = "Run at interrupte level";
}
CONSTANT PLUGS_DEBUG
{
value = "1";
comment = "Support debug routines";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
}
}
MASTER custom_instruction_master
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "nios_custom_instruction";
Data_Width = "32";
Address_Width = "8";
Max_Address_Width = "8";
Base_Address = "N/A";
Is_Visible = "0";
Is_Custom_Instruction = "0";
Is_Enabled = "0";
}
}
PORT_WIRING
{
PORT jtag_debug_trigout
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_clk
{
width = "1";
direction = "output";
Is_Enabled = "0";
}
PORT jtag_debug_offchip_trace_data
{
width = "18";
direction = "output";
Is_Enabled = "0";
}
PORT clkx2
{
width = "1";
direction = "input";
Is_Enabled = "0";
}
}
SIMULATION
{
DISPLAY
{
SIGNAL aaa
{
format = "Logic";
name = "i_readdata";
radix = "hexadecimal";
}
SIGNAL aab
{
format = "Logic";
name = "i_readdatavalid";
radix = "hexadecimal";
}
SIGNAL aac
{
format = "Logic";
name = "i_waitrequest";
radix = "hexadecimal";
}
SIGNAL aad
{
format = "Logic";
name = "i_address";
radix = "hexadecimal";
}
SIGNAL aae
{
format = "Logic";
name = "i_read";
radix = "hexadecimal";
}
SIGNAL aaf
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aag
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aah
{
format = "Logic";
name = "d_readdata";
radix = "hexadecimal";
}
SIGNAL aai
{
format = "Logic";
name = "d_waitrequest";
radix = "hexadecimal";
}
SIGNAL aaj
{
format = "Logic";
name = "d_irq";
radix = "hexadecimal";
}
SIGNAL aak
{
format = "Logic";
name = "d_address";
radix = "hexadecimal";
}
SIGNAL aal
{
format = "Logic";
name = "d_byteenable";
radix = "hexadecimal";
}
SIGNAL aam
{
format = "Logic";
name = "d_read";
radix = "hexadecimal";
}
SIGNAL aan
{
format = "Logic";
name = "d_write";
radix = "hexadecimal";
}
SIGNAL aao
{
format = "Logic";
name = "d_writedata";
radix = "hexadecimal";
}
SIGNAL aap
{
format = "Divider";
name = "base pipeline";
radix = "";
}
SIGNAL aaq
{
format = "Logic";
name = "clk";
radix = "hexadecimal";
}
SIGNAL aar
{
format = "Logic";
name = "reset_n";
radix = "hexadecimal";
}
SIGNAL aas
{
format = "Logic";
name = "M_stall";
radix = "hexadecimal";
}
SIGNAL aat
{
format = "Logic";
name = "F_pcb_nxt";
radix = "hexadecimal";
}
SIGNAL aau
{
format = "Logic";
name = "F_pcb";
radix = "hexadecimal";
}
SIGNAL aav
{
format = "Logic";
name = "D_pcb";
radix = "hexadecimal";
}
SIGNAL aaw
{
format = "Logic";
name = "E_pcb";
radix = "hexadecimal";
}
SIGNAL aax
{
format = "Logic";
name = "M_pcb";
radix = "hexadecimal";
}
SIGNAL aay
{
format = "Logic";
name = "W_pcb";
radix = "hexadecimal";
}
SIGNAL aaz
{
format = "Logic";
name = "F_vinst";
radix = "ascii";
}
SIGNAL aba
{
format = "Logic";
name = "D_vinst";
radix = "ascii";
}
SIGNAL abb
{
format = "Logic";
name = "E_vinst";
radix = "ascii";
}
SIGNAL abc
{
format = "Logic";
name = "M_vinst";
radix = "ascii";
}
SIGNAL abd
{
format = "Logic";
name = "W_vinst";
radix = "ascii";
}
SIGNAL abe
{
format = "Logic";
name = "F_inst_ram_hit";
radix = "hexadecimal";
}
SIGNAL abf
{
format = "Logic";
name = "F_issue";
radix = "hexadecimal";
}
SIGNAL abg
{
format = "Logic";
name = "F_kill";
radix = "hexadecimal";
}
SIGNAL abh
{
format = "Logic";
name = "D_kill";
radix = "hexadecimal";
}
SIGNAL abi
{
format = "Logic";
name = "D_refetch";
radix = "hexadecimal";
}
SIGNAL abj
{
format = "Logic";
name = "D_issue";
radix = "hexadecimal";
}
SIGNAL abk
{
format = "Logic";
name = "D_valid";
radix = "hexadecimal";
}
SIGNAL abl
{
format = "Logic";
name = "E_valid";
radix = "hexadecimal";
}
SIGNAL abm
{
format = "Logic";
name = "M_valid";
radix = "hexadecimal";
}
SIGNAL abn
{
format = "Logic";
name = "W_valid";
radix = "hexadecimal";
}
SIGNAL abo
{
format = "Logic";
name = "W_wr_dst_reg";
radix = "hexadecimal";
}
SIGNAL abp
{
format = "Logic";
name = "W_dst_regnum";
radix = "hexadecimal";
}
SIGNAL abq
{
format = "Logic";
name = "W_wr_data";
radix = "hexadecimal";
}
SIGNAL abr
{
format = "Logic";
name = "F_en";
radix = "hexadecimal";
}
SIGNAL abs
{
format = "Logic";
name = "D_en";
radix = "hexadecimal";
}
SIGNAL abt
{
format = "Logic";
name = "E_en";
radix = "hexadecimal";
}
SIGNAL abu
{
format = "Logic";
name = "M_en";
radix = "hexadecimal";
}
SIGNAL abv
{
format = "Logic";
name = "F_iw";
radix = "hexadecimal";
}
SIGNAL abw
{
format = "Logic";
name = "D_iw";
radix = "hexadecimal";
}
SIGNAL abx
{
format = "Logic";
name = "E_iw";
radix = "hexadecimal";
}
SIGNAL aby
{
format = "Logic";
name = "E_valid_prior_to_hbreak";
radix = "hexadecimal";
}
SIGNAL abz
{
format = "Logic";
name = "M_pipe_flush_nxt";
radix = "hexadecimal";
}
SIGNAL aca
{
format = "Logic";
name = "M_pipe_flush_baddr_nxt";
radix = "hexadecimal";
}
SIGNAL acb
{
format = "Logic";
name = "M_status_reg_pie";
radix = "hexadecimal";
}
SIGNAL acc
{
format = "Logic";
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