smartsopc_board_cyclone_1c66_log.txt

sopc开发板标准NIOSII模块

Altera SOPC Builder Version 5.00 Build 168
Copyright (c) 1999-2005 Altera Corporation.  All rights reserved.


# 2005.12.23 19:14:55 (*) mk_custom_sdk starting
# 2005.12.23 19:14:55 (*) Reading project F:/DeviceSOPC/smartsopc_board_cyclone_1c6/system/smartsopc_board_cyclone_1c6.ptf.

# 2005.12.23 19:14:56 (*) Finding all CPUs
# 2005.12.23 19:14:56 (*) Finding all available components

# 2005.12.23 19:14:56 (*) Found 59 components

# 2005.12.23 19:14:59 (*) Finding all peripherals

# 2005.12.23 19:14:59 (*) Finding software components

# 2005.12.23 19:15:00 (*) (Legacy SDK Generation Skipped)
# 2005.12.23 19:15:00 (*) (All TCL Script Generation Skipped)
# 2005.12.23 19:15:00 (*) (No Libraries Built)
# 2005.12.23 19:15:00 (*) (Contents Generation Skipped)
# 2005.12.23 19:15:00 (*) mk_custom_sdk finishing

# 2005.12.23 19:15:00 (*) Starting generation for system: smartsopc_board_cyclone_1c6.

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# 2005.12.23 19:15:06 (*) Running Generator Program for cpu_0

# 2005.12.23 19:15:11 (*)   Checking for plaintext license.
# 2005.12.23 19:15:11 (*)   Plaintext license not found.
# 2005.12.23 19:15:11 (*)   Checking for encrypted license (non-evaluation).
# 2005.12.23 19:15:12 (*)   Encrypted license found.  SOF will not be time-limited.
# 2005.12.23 19:15:27 (*)   Creating encrypted HDL

# 2005.12.23 19:15:31 (*) Running Generator Program for firmware_ROM

# 2005.12.23 19:15:34 (*) Running Generator Program for data_RAM

# 2005.12.23 19:15:36 (*) Running Generator Program for payload_buffer

# 2005.12.23 19:15:39 (*) Running Generator Program for jtag_uart_0

# 2005.12.23 19:15:42 (*) Running Generator Program for sysid

# 2005.12.23 19:15:45 (*) Running Generator Program for asmi

# 2005.12.23 19:15:48 (*) Running Generator Program for Board_System

# 2005.12.23 19:15:49 (*) Now generating custom board component and flash programmer design.
# 2005.12.23 19:15:49 (*) After generation is complete, you must do the following next steps:
# 2005.12.23 19:15:49 (*)  1.) Update the system symbol in QuartusII
# 2005.12.23 19:15:49 (*)  2.) Add flash pins to the .bdf schematic file and connect them to the flash
# 2005.12.23 19:15:49 (*)       ports on the updated symbol.
# 2005.12.23 19:15:49 (*)  3.) Add pins to the .bdf schematic file to dissable any other external devices

# 2005.12.23 19:15:49 (*)       that are on the same tri-state bus as flash.
# 2005.12.23 19:15:49 (*)   4.) Assign the schematic pins you added to the associated device pins that
# 2005.12.23 19:15:49 (*)       connect to the external devices
# 2005.12.23 19:15:49 (*)  5.) Compile the design in QuartusII.
# 2005.12.23 19:15:49 (*) It is important that you consult the document "NiosII Flash Programmer User Guide",
# 2005.12.23 19:15:49 (*)  available at www.altera.com, before attempting to port the NiosII Flash Programmer

# 2005.12.23 19:15:49 (*)  to custom boards.


# 2005.12.23 19:15:50 (*) Running Generator Program for cfi_flash_0


# 2005.12.23 19:15:52 (*) Making arbitration and system (top) modules.

# 2005.12.23 19:16:11 (*) Generating Quartus symbol for top level: smartsopc_board_cyclone_1c6

# 2005.12.23 19:16:11 (*) Symbol F:/DeviceSOPC/smartsopc_board_cyclone_1c6/system/smartsopc_board_cyclone_1c6.bsf already exists, no need to regenerate
# 2005.12.23 19:16:11 (*) Creating command-line system-generation script: F:/DeviceSOPC/smartsopc_board_cyclone_1c6/system/smartsopc_board_cyclone_1c6_generation_script

# 2005.12.23 19:16:12 (*) Running setup for HDL simulator: modelsim


# 2005.12.23 19:16:12 (*) Setting up Quartus with smartsopc_board_cyclone_1c6_setup_quartus.tcl
c:/altera/quartus50/bin/quartus_sh -t smartsopc_board_cyclone_1c6_setup_quartus.tcl


Info: *******************************************************************
Info: Running Quartus II Shell
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
    Info: Copyright (C) 1991-2005 Altera Corporation. All rights reserved.
    Info: Your use of Altera Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic       
    Info: functions, and any output files any of the foregoing           
    Info: (including device programming or simulation files), and any    

    Info: associated documentation or information are expressly subject  
    Info: to the terms and conditions of the Altera Program License      
    Info: Subscription Agreement, Altera MegaCore Function License       
    Info: Agreement, or other applicable license agreement, including,   
    Info: without limitation, that your use is for the sole purpose of   
    Info: programming logic devices manufactured by Altera and sold by   
    Info: Altera or its authorized distributors.  Please refer to the    

    Info: applicable agreement for further details.
    Info: Processing started: Fri Dec 23 19:16:14 2005
Info: Command: quartus_sh -t smartsopc_board_cyclone_1c6_setup_quartus.tcl

Info: Evaluation of Tcl script smartsopc_board_cyclone_1c6_setup_quartus.tcl was successful

# 2005.12.23 19:16:16 (*) Completed generation for system: smartsopc_board_cyclone_1c6.
# 2005.12.23 19:16:16 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
  SOPC Builder database : F:/DeviceSOPC/smartsopc_board_cyclone_1c6/system/smartsopc_board_cyclone_1c6.ptf 
  System HDL Model : F:/DeviceSOPC/smartsopc_board_cyclone_1c6/system/smartsopc_board_cyclone_1c6.v 
  System Generation Script : F:/DeviceSOPC/smartsopc_board_cyclone_1c6/system/smartsopc_board_cyclone_1c6_generation_script 

# 2005.12.23 19:16:16 (*) SUCCESS: SYSTEM GENERATION COMPLETED.


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