smartsopc_board_cyclone_1c6.v

sopc开发板标准NIOSII模块

  input   [ 31: 0] sysid_control_slave_readdata_from_sa;

  wire    [ 22: 0] cpu_0_data_master_address_to_slave;
  reg     [  1: 0] cpu_0_data_master_dbs_address;
  wire    [  1: 0] cpu_0_data_master_dbs_increment;
  wire    [ 15: 0] cpu_0_data_master_dbs_write_16;
  wire    [ 31: 0] cpu_0_data_master_irq;
  reg              cpu_0_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_0_data_master_readdata;
  wire             cpu_0_data_master_reset_n;
  wire             cpu_0_data_master_run;
  reg              cpu_0_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             dummy_sink;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [ 31: 0] p1_registered_cpu_0_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  reg     [ 31: 0] registered_cpu_0_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~cpu_0_data_master_qualified_request_asmi_asmi_control_port | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_asmi_asmi_control_port | ~cpu_0_data_master_write | (1 & 1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_data_RAM_s1 | registered_cpu_0_data_master_read_data_valid_data_RAM_s1 | ~cpu_0_data_master_requests_data_RAM_s1) & (cpu_0_data_master_granted_data_RAM_s1 | ~cpu_0_data_master_qualified_request_data_RAM_s1) & ((~cpu_0_data_master_qualified_request_data_RAM_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_data_RAM_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_data_RAM_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_firmware_ROM_s1 | registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 | ~cpu_0_data_master_requests_firmware_ROM_s1) & (cpu_0_data_master_granted_firmware_ROM_s1 | ~cpu_0_data_master_qualified_request_firmware_ROM_s1) & ((~cpu_0_data_master_qualified_request_firmware_ROM_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_firmware_ROM_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_firmware_ROM_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_read | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_write | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_payload_buffer_s1 | (registered_cpu_0_data_master_read_data_valid_payload_buffer_s1 & cpu_0_data_master_dbs_address[1]) | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_payload_buffer_s1 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_payload_buffer_s1) & (cpu_0_data_master_granted_payload_buffer_s1 | ~cpu_0_data_master_qualified_request_payload_buffer_s1);

  //cascaded wait assignment, which is an e_assign
  assign cpu_0_data_master_run = r_0 & r_1;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = ((~cpu_0_data_master_qualified_request_payload_buffer_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_payload_buffer_s1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_payload_buffer_s1 | ~cpu_0_data_master_write | (1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_cfi_flash_0_s1 | (registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 & cpu_0_data_master_dbs_address[1]) | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_0_s1 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_cfi_flash_0_s1) & (cpu_0_data_master_qualified_request_cfi_flash_1_s1 | (registered_cpu_0_data_master_read_data_valid_cfi_flash_1_s1 & cpu_0_data_master_dbs_address[1]) | (cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_1_s1 & cpu_0_data_master_dbs_address[1]) | ~cpu_0_data_master_requests_cfi_flash_1_s1) & (cpu_0_data_master_granted_cfi_flash_0_s1 | ~cpu_0_data_master_qualified_request_cfi_flash_0_s1) & (cpu_0_data_master_granted_cfi_flash_1_s1 | ~cpu_0_data_master_qualified_request_cfi_flash_1_s1) & ((~cpu_0_data_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_cfi_flash_0_s1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cfi_flash_0_s1 | ~cpu_0_data_master_write | (1 & cfi_flash_0_s1_wait_counter_eq_1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write))) & ((~cpu_0_data_master_qualified_request_cfi_flash_1_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_cfi_flash_1_s1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cfi_flash_1_s1 | ~cpu_0_data_master_write | (1 & cfi_flash_1_s1_wait_counter_eq_1 & (cpu_0_data_master_dbs_address[1]) & cpu_0_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[22 : 0];

  //dummy sink, which is an e_mux
  assign dummy_sink = cpu_0_data_master_address_to_slave |
    cpu_0_data_master_requests_asmi_asmi_control_port |
    cpu_0_data_master_qualified_request_asmi_asmi_control_port |
    d1_asmi_asmi_control_port_end_xfer |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_read_data_valid_data_RAM_s1 |
    cpu_0_data_master_requests_data_RAM_s1 |
    cpu_0_data_master_qualified_request_data_RAM_s1 |
    d1_data_RAM_s1_end_xfer |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_read_data_valid_firmware_ROM_s1 |
    cpu_0_data_master_requests_firmware_ROM_s1 |
    cpu_0_data_master_qualified_request_firmware_ROM_s1 |
    d1_firmware_ROM_s1_end_xfer |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave |
    cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave |
    d1_jtag_uart_0_avalon_jtag_slave_end_xfer |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_read_data_valid_payload_buffer_s1 |
    cpu_0_data_master_requests_payload_buffer_s1 |
    cpu_0_data_master_qualified_request_payload_buffer_s1 |
    d1_payload_buffer_s1_end_xfer |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_requests_sysid_control_slave |
    cpu_0_data_master_qualified_request_sysid_control_slave |
    d1_sysid_control_slave_end_xfer |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_read_data_valid_cfi_flash_0_s1 |
    cpu_0_data_master_requests_cfi_flash_0_s1 |
    cpu_0_data_master_qualified_request_cfi_flash_0_s1 |
    cpu_0_data_master_address_to_slave |
    cpu_0_data_master_read_data_valid_cfi_flash_1_s1 |
    cpu_0_data_master_requests_cfi_flash_1_s1 |
    cpu_0_data_master_qualified_request_cfi_flash_1_s1 |
    d1_tri_state_bridge_0_avalon_slave_end_xfer |
    cfi_flash_0_s1_wait_counter_eq_0 |
    cfi_flash_1_s1_wait_counter_eq_0;

  //cpu_0/data_master readdata mux, which is an e_mux
  assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_asmi_asmi_control_port}} | asmi_asmi_control_port_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_data_RAM_s1}} | data_RAM_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_firmware_ROM_s1}} | firmware_ROM_s1_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
    ({32 {~cpu_0_data_master_requests_payload_buffer_s1}} | {payload_buffer_s1_readdata_from_sa,
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_0_data_master_requests_sysid_control_slave}} | sysid_control_slave_readdata_from_sa) &
    ({32 {~cpu_0_data_master_requests_cfi_flash_0_s1}} | {incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_0_data_master_requests_cfi_flash_1_s1}} | {incoming_tri_state_bridge_0_data_with_Xs_converted_to_0,
    dbs_16_reg_segment_0});

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_waitrequest <= ~0;
      else if (1)
          cpu_0_data_master_waitrequest <= ~((~(cpu_0_data_master_read | cpu_0_data_master_write))? 0: (cpu_0_data_master_run & cpu_0_data_master_waitrequest));
    end


  //cpu_0_data_master_reset_n assignment, which is an e_assign
  assign cpu_0_data_master_reset_n = reset_n;

  //irq assign, which is an e_assign
  assign cpu_0_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    asmi_asmi_control_port_irq_from_sa,
    jtag_uart_0_avalon_jtag_slave_irq_from_sa};

  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_0_data_master_readdata <= 0;
      else if (1)
          registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_0_data_master_readdata = {32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | jtag_uart_0_avalon_jtag_slave_readdata_from_sa;

  //no_byte_enables_and_last_term, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_0_data_master_no_byte_enables_and_last_term <= 0;
      else if (1)
          cpu_0_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
    end


  //compute the last dbs term, which is an e_mux
  assign last_dbs_term_and_run = (cpu_0_data_master_requests_payload_buffer_s1)? (((cpu_0_data_master_dbs_address == 2'b10) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_payload_buffer_s1)) :
    (cpu_0_data_master_requests_cfi_flash_0_s1)? (((cpu_0_data_master_dbs_address == 2'b10) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_0_s1)) :
    (((cpu_0_data_master_dbs_address == 2'b10) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_1_s1));

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_payload_buffer_s1 & cpu_0_data_master_write & !cpu_0_data_master_byteenable_payload_buffer_s1)) |
    cpu_0_data_master_read_data_valid_payload_buffer_s1 |
    (cpu_0_data_master_granted_payload_buffer_s1 & cpu_0_data_master_write & 1 & 1) |
    (((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_cfi_flash_0_s1 & cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_0_s1)) |
    (((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_cfi_flash_1_s1 & cpu_0_data_master_write & !cpu_0_data_master_byteenable_cfi_flash_1_s1)) |
    cpu_0_data_master_read_data_valid_cfi_flash_0_s1 |
    ((cpu_0_data_master_granted_cfi_flash_0_s1 & cpu_0_data_master_write & 1 & 1 & ({cfi_flash_0_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer}))) |
    cpu_0_data_master_read_data_valid_cfi_flash_1_s1 |
    ((cpu_0_data_master_granted_cfi_flash_1_s1 & cpu_0_data_master_write & 1 & 1 & ({cfi_flash_1_s1_wait_counter_eq_0 & ~d1_tri_state_bridge_0_avalon_slave_end_xfer})));

  //input to dbs-16 stored 0, which is an e_mux
  assign p1_dbs_16_reg_segment_0 = (cpu_0_data_master_requests_payload_buffer_s1)? payload_buffer_s1_readdata_from_sa :
    (cpu_0_data_master_requests_cfi_flash_0_s1)? incoming_tri_state_bridge_0_data_with_Xs_converted_to_0 :
    incoming_tri_state_bridge_0_data_with_Xs_converted_to_0;

  //dbs register for dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_16_reg_segment_0 <= 0;
      else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1]) == 0))
          dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
    end


  //mux write dbs 1, which is an e_mux
  assign cpu_0_data_master_dbs_write_16 = (cpu_0_data_master_dbs_address[1])? cpu_0_data_master_writedata[31 : 16] :
    (~(cpu_0_data_master_dbs_address[1]))? cpu_0_data_master_writedata[15 : 0] :
    (cpu_0_data_master_dbs_address[1])? cpu_0_data_master_writedata[31 : 16] :
    (~(cpu_0_data_master_dbs_address[1]))? cpu_0_data_master_writedata[15 : 0] :
    (cpu_0_data_master_dbs_address[1])? cpu_0_data_master_writedata[31 : 16] :
    cpu_0_data_master_writedata[15 : 0];

  //dbs count increment, which is an e_mux
  assign cpu_0_data_master_dbs_increment = (cpu_0_data_master_requests_payload_buffer_s1)? 2 :
    (cpu_0_data_master_requests_cfi_flash_0_s1)? 2 :
    (cpu_0_data_master_requests_cfi_flash_1_s1)? 2 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_0_data_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_0_data_master_dbs_address + cpu_0_data_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable &