smartsopc_board_cyclone_1c6.v

sopc开发板标准NIOSII模块

//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 100ps
// synthesis translate_on
module asmi_asmi_control_port_arbitrator (
                                           // inputs:
                                            asmi_asmi_control_port_dataavailable,
                                            asmi_asmi_control_port_endofpacket,
                                            asmi_asmi_control_port_irq,
                                            asmi_asmi_control_port_readdata,
                                            asmi_asmi_control_port_readyfordata,
                                            clk,
                                            cpu_0_data_master_address_to_slave,
                                            cpu_0_data_master_read,
                                            cpu_0_data_master_write,
                                            cpu_0_data_master_writedata,
                                            reset_n,

                                           // outputs:
                                            asmi_asmi_control_port_address,
                                            asmi_asmi_control_port_chipselect,
                                            asmi_asmi_control_port_dataavailable_from_sa,
                                            asmi_asmi_control_port_endofpacket_from_sa,
                                            asmi_asmi_control_port_irq_from_sa,
                                            asmi_asmi_control_port_read_n,
                                            asmi_asmi_control_port_readdata_from_sa,
                                            asmi_asmi_control_port_readyfordata_from_sa,
                                            asmi_asmi_control_port_reset_n,
                                            asmi_asmi_control_port_write_n,
                                            asmi_asmi_control_port_writedata,
                                            cpu_0_data_master_granted_asmi_asmi_control_port,
                                            cpu_0_data_master_qualified_request_asmi_asmi_control_port,
                                            cpu_0_data_master_read_data_valid_asmi_asmi_control_port,
                                            cpu_0_data_master_requests_asmi_asmi_control_port,
                                            d1_asmi_asmi_control_port_end_xfer
                                         );

  output  [  2: 0] asmi_asmi_control_port_address;
  output           asmi_asmi_control_port_chipselect;
  output           asmi_asmi_control_port_dataavailable_from_sa;
  output           asmi_asmi_control_port_endofpacket_from_sa;
  output           asmi_asmi_control_port_irq_from_sa;
  output           asmi_asmi_control_port_read_n;
  output  [ 15: 0] asmi_asmi_control_port_readdata_from_sa;
  output           asmi_asmi_control_port_readyfordata_from_sa;
  output           asmi_asmi_control_port_reset_n;
  output           asmi_asmi_control_port_write_n;
  output  [ 15: 0] asmi_asmi_control_port_writedata;
  output           cpu_0_data_master_granted_asmi_asmi_control_port;
  output           cpu_0_data_master_qualified_request_asmi_asmi_control_port;
  output           cpu_0_data_master_read_data_valid_asmi_asmi_control_port;
  output           cpu_0_data_master_requests_asmi_asmi_control_port;
  output           d1_asmi_asmi_control_port_end_xfer;
  input            asmi_asmi_control_port_dataavailable;
  input            asmi_asmi_control_port_endofpacket;
  input            asmi_asmi_control_port_irq;
  input   [ 15: 0] asmi_asmi_control_port_readdata;
  input            asmi_asmi_control_port_readyfordata;
  input            clk;
  input   [ 22: 0] cpu_0_data_master_address_to_slave;
  input            cpu_0_data_master_read;
  input            cpu_0_data_master_write;
  input   [ 31: 0] cpu_0_data_master_writedata;
  input            reset_n;

  wire    [  2: 0] asmi_asmi_control_port_address;
  wire             asmi_asmi_control_port_allgrants;
  wire             asmi_asmi_control_port_allow_new_arb_cycle;
  wire             asmi_asmi_control_port_any_continuerequest;
  wire             asmi_asmi_control_port_arb_counter_enable;
  reg     [  1: 0] asmi_asmi_control_port_arb_share_counter;
  wire    [  1: 0] asmi_asmi_control_port_arb_share_counter_next_value;
  wire    [  1: 0] asmi_asmi_control_port_arb_share_set_values;
  wire             asmi_asmi_control_port_arbitration_holdoff_internal;
  wire             asmi_asmi_control_port_beginbursttransfer_internal;
  wire             asmi_asmi_control_port_begins_xfer;
  wire             asmi_asmi_control_port_chipselect;
  wire             asmi_asmi_control_port_dataavailable_from_sa;
  wire             asmi_asmi_control_port_end_xfer;
  wire             asmi_asmi_control_port_endofpacket_from_sa;
  wire             asmi_asmi_control_port_firsttransfer;
  wire             asmi_asmi_control_port_grant_vector;
  wire             asmi_asmi_control_port_in_a_read_cycle;
  wire             asmi_asmi_control_port_in_a_write_cycle;
  wire             asmi_asmi_control_port_irq_from_sa;
  wire             asmi_asmi_control_port_master_qreq_vector;
  wire             asmi_asmi_control_port_read_n;
  wire    [ 15: 0] asmi_asmi_control_port_readdata_from_sa;
  wire             asmi_asmi_control_port_readyfordata_from_sa;
  wire             asmi_asmi_control_port_reset_n;
  reg              asmi_asmi_control_port_slavearbiterlockenable;
  wire             asmi_asmi_control_port_waits_for_read;
  wire             asmi_asmi_control_port_waits_for_write;
  wire             asmi_asmi_control_port_write_n;
  wire    [ 15: 0] asmi_asmi_control_port_writedata;
  wire             cpu_0_data_master_arbiterlock;
  wire             cpu_0_data_master_continuerequest;
  wire             cpu_0_data_master_granted_asmi_asmi_control_port;
  wire             cpu_0_data_master_qualified_request_asmi_asmi_control_port;
  wire             cpu_0_data_master_read_data_valid_asmi_asmi_control_port;
  wire             cpu_0_data_master_requests_asmi_asmi_control_port;
  wire             cpu_0_data_master_saved_grant_asmi_asmi_control_port;
  reg              d1_asmi_asmi_control_port_end_xfer;
  reg              d1_reasons_to_wait;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             wait_for_asmi_asmi_control_port_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~asmi_asmi_control_port_end_xfer;
    end


  assign asmi_asmi_control_port_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_asmi_asmi_control_port));
  //assign asmi_asmi_control_port_readdata_from_sa = asmi_asmi_control_port_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign asmi_asmi_control_port_readdata_from_sa = asmi_asmi_control_port_readdata;

  assign cpu_0_data_master_requests_asmi_asmi_control_port = ({cpu_0_data_master_address_to_slave[22 : 5] , 5'b0} == 23'h60000) & (cpu_0_data_master_read | cpu_0_data_master_write);
  //assign asmi_asmi_control_port_dataavailable_from_sa = asmi_asmi_control_port_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign asmi_asmi_control_port_dataavailable_from_sa = asmi_asmi_control_port_dataavailable;

  //assign asmi_asmi_control_port_readyfordata_from_sa = asmi_asmi_control_port_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign asmi_asmi_control_port_readyfordata_from_sa = asmi_asmi_control_port_readyfordata;

  //asmi_asmi_control_port_arb_share_counter set values, which is an e_mux
  assign asmi_asmi_control_port_arb_share_set_values = 1;

  //asmi_asmi_control_port_arb_share_counter_next_value assignment, which is an e_assign
  assign asmi_asmi_control_port_arb_share_counter_next_value = asmi_asmi_control_port_firsttransfer ? (asmi_asmi_control_port_arb_share_set_values - 1) : |asmi_asmi_control_port_arb_share_counter ? (asmi_asmi_control_port_arb_share_counter - 1) : 0;

  //asmi_asmi_control_port_allgrants all slave grants, which is an e_mux
  assign asmi_asmi_control_port_allgrants = |asmi_asmi_control_port_grant_vector;

  //asmi_asmi_control_port_end_xfer assignment, which is an e_assign
  assign asmi_asmi_control_port_end_xfer = ~(asmi_asmi_control_port_waits_for_read | asmi_asmi_control_port_waits_for_write);

  //asmi_asmi_control_port_arb_share_counter arbitration counter enable, which is an e_assign
  assign asmi_asmi_control_port_arb_counter_enable = asmi_asmi_control_port_end_xfer & asmi_asmi_control_port_allgrants;

  //asmi_asmi_control_port_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          asmi_asmi_control_port_arb_share_counter <= 0;
      else if (asmi_asmi_control_port_arb_counter_enable)
          asmi_asmi_control_port_arb_share_counter <= asmi_asmi_control_port_arb_share_counter_next_value;
    end


  //asmi_asmi_control_port_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          asmi_asmi_control_port_slavearbiterlockenable <= 0;
      else if (|asmi_asmi_control_port_master_qreq_vector & asmi_asmi_control_port_end_xfer)
          asmi_asmi_control_port_slavearbiterlockenable <= |asmi_asmi_control_port_arb_share_counter_next_value;
    end


  //cpu_0/data_master asmi/asmi_control_port arbiterlock, which is an e_assign
  assign cpu_0_data_master_arbiterlock = asmi_asmi_control_port_slavearbiterlockenable & cpu_0_data_master_continuerequest;

  //asmi_asmi_control_port_any_continuerequest at least one master continues requesting, which is an e_assign
  assign asmi_asmi_control_port_any_continuerequest = 0;

  //cpu_0_data_master_continuerequest continued request, which is an e_assign
  assign cpu_0_data_master_continuerequest = 0;

  assign cpu_0_data_master_qualified_request_asmi_asmi_control_port = cpu_0_data_master_requests_asmi_asmi_control_port;
  //asmi_asmi_control_port_writedata mux, which is an e_mux
  assign asmi_asmi_control_port_writedata = cpu_0_data_master_writedata;

  //assign asmi_asmi_control_port_endofpacket_from_sa = asmi_asmi_control_port_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign asmi_asmi_control_port_endofpacket_from_sa = asmi_asmi_control_port_endofpacket;

  //master is always granted when requested
  assign cpu_0_data_master_granted_asmi_asmi_control_port = cpu_0_data_master_qualified_request_asmi_asmi_control_port;

  //cpu_0/data_master saved-grant asmi/asmi_control_port, which is an e_assign
  assign cpu_0_data_master_saved_grant_asmi_asmi_control_port = cpu_0_data_master_requests_asmi_asmi_control_port;

  //allow new arb cycle for asmi/asmi_control_port, which is an e_assign
  assign asmi_asmi_control_port_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign asmi_asmi_control_port_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign asmi_asmi_control_port_master_qreq_vector = 1;

  //asmi_asmi_control_port_reset_n assignment, which is an e_assign
  assign asmi_asmi_control_port_reset_n = reset_n;