📄 fet140_tb_01.s43
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;******************************************************************************
; MSP-FET430P140 Demo - Timer_B, Toggle P1.0, CCR0 Cont. Mode ISR, DCO SMCLK
;
; Description: Toggle P1.0 using software and TB_0 ISR. Toggles every
; 50000 SMCLK cycles. SMCLK provides clock source for TBCLK.
; During the TB_0 ISR, P1.0 is toggled and 50000 clock cycles are added to
; CCR0. TB_0 ISR is triggered every 50000 cycles. CPU is normally off and
; used only during TB_ISR.
; ACLK = n/a, MCLK = SMCLK = TBCLK = default DCO ~800kHz
;
; MSP430F149
; -----------------
; /|\| XIN|-
; | | |
; --|RST XOUT|-
; | |
; | P1.0|-->LED
;
; M. Buccini
; Texas Instruments Inc.
; Feb 2005
; Built with IAR Embedded Workbench Version: 3.21A
;******************************************************************************
#include <msp430x14x.h>
;------------------------------------------------------------------------------
ORG 01100h ; Progam Start
;------------------------------------------------------------------------------
RESET mov.w #0A00h,SP ; Initialize stackpointer
StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT
SetupP1 bis.b #001h,&P1DIR ; P1.0 output
SetupC0 mov.w #CCIE,&TBCCTL0 ; CCR0 interrupt enabled
mov.w #50000,&TBCCR0 ;
SetupTB mov.w #TBSSEL_2+MC_2,&TBCTL ; SMCLK, contmode
;
Mainloop bis.w #CPUOFF+GIE,SR ; CPU off, interrupts enabled
nop ; Required only for debugger
;
;------------------------------------------------------------------------------
TB0_ISR; Toggle P1.0
;------------------------------------------------------------------------------
xor.b #001h,&P1OUT ; Toggle P1.0
add.w #50000,&TBCCR0 ; Add Offset to CCR0
reti ;
;
;------------------------------------------------------------------------------
; Interrupt Vectors
;------------------------------------------------------------------------------
ORG 0FFFEh ; MSP430 RESET Vector
DW RESET ;
ORG 0FFFAh ; Timer_B0 Vector
DW TB0_ISR ;
END
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