sddma.c

SD卡驱动程序。周立功单片机公司开发板提供的标准例程。

/****************************************Copyright (c)**************************************************
**                               Guangzhou ZLG-MCU Development Co.,LTD.
**                                      graduate school
**                                 http://www.zlgmcu.com
**
**--------------File Info-------------------------------------------------------------------------------
** File name:			sdhal.c
** Last modified Date:	2005-3-11
** Last Version:		V2.0
** Descriptions:		SD/MMC卡读写模块: 硬件抽象层 ---- SPI操作函数
**						Soft Packet of SD/MMC Card: hard abstrast layer ---- function of SPI operation
**
**------------------------------------------------------------------------------------------------------
** Created by:			Ming Yuan Zheng
** Created date:		2005-1-6
** Version:				V1.0
** Descriptions:		The original version
**
**------------------------------------------------------------------------------------------------------
** Modified by:			
** Modified date:		
** Version:				
** Descriptions:		
**
**------------------------------------------------------------------------------------------------------
** Modified by: 
** Modified date:
** Version:	
** Descriptions: 
**
********************************************************************************************************/


#include "sdconfig.h"


#if MCI_DMA_ENABLED


/*******************************************************************************************************************
** 函数名称: DMA_Init()				
**
** 功能描述: LPC23xx DMA控制器初始化
**
** 输　  入: INT32U ChannelNum: DMA 控制器通道号 
**	         INT32U DMAMode:    DMA 模式
** 输 　 出: 无
**
** 返 回 值: TRUE:   正确;    FALSE:   错误
********************************************************************************************************************/
INT32U DMA_Init(INT32U ChannelNum, INT32U DMAMode)
{
	/* USB RAM is used for test.
	Please note, Ethernet has its own SRAM, but GPDMA can't access
	that. GPDMA can access USB SRAM and IRAM. Ethernet DMA controller can 
	access both IRAM and Ethernet SRAM. */
	if ( ChannelNum == 0 )
	{
		DMACIntErrClr = 0x01;   
		if ( DMAMode == M2M )
		{
			/* Ch0 is set for M2M tranfer from AHB1 to AHB2 SRAM */
			DMACC0SrcAddr = DMA_SRC;
			DMACC0DestAddr = DMA_DST;
			/* Terminal Count Int enable */
			DMACC0Control = (DMA_SIZE & 0x0FFF) | (0x04 << 12) | (0x04 << 15) 
				| (0x02 << 18) | (0x02 << 21) | (1 << 26) | (1 << 27) | 0x80000000;	
		}
		else if ( DMAMode == M2P )
		{
			/* Ch0 set for M2P transfer from mempry to MCI FIFO. */
			DMACC0SrcAddr = DMA_SRC;
			DMACC0DestAddr = DMA_MCIFIFO;
			/* The burst size is set to 8, the size is 8 bit too. */
			/* Terminal Count Int enable */
			DMACC0Control = (DMA_SIZE & 0x0FFF) | (0x01 << 12) | (0x02 << 15)
				| (0x02 << 18) | (0x02 << 21) | (1 << 26) | 0x80000000;
		}
		else if ( DMAMode == P2M )
		{
			/* Ch0 set for P2M transfer from MCI FIFO to memory. */
			DMACC0SrcAddr = DMA_MCIFIFO;
			DMACC0DestAddr = DMA_DST;
			/* The burst size is set to 8, the size is 8 bit too. */
			/* Terminal Count Int enable */
			DMACC0Control = (DMA_SIZE & 0x0FFF) | (0x04 << 12) | (0x04 << 15)
				| (0x02 << 18) | (0x02 << 21) | (1 << 27) | 0x80000000;
		}
		else
		{
			return ( FALSE );
		}
	}
	else if ( ChannelNum == 1 )
	{   
		DMACIntErrClr = 0x02;
		if ( DMAMode == M2M )
		{
			/* Ch1 is set for M2M tranfer */
			DMACC1SrcAddr = DMA_SRC;
			DMACC1DestAddr = DMA_DST;
			/* Terminal Count Int enable */
			DMACC1Control = (DMA_SIZE & 0x0FFF) | (0x04 << 12) | (0x04 << 15) 
				| (0x02 << 18) | (0x02 << 21) | (1 << 26) | (1 << 27) | 0x80000000;	
		}
		else if ( DMAMode == M2P )
		{
			/* Ch1 set for M2P transfer from mempry to MCI FIFO. */
			DMACC1SrcAddr = DMA_SRC;
			DMACC1DestAddr = DMA_MCIFIFO;
			/* The burst size is set to 8, the size is 8 bit too. */
			/* Terminal Count Int enable */
			DMACC1Control = (DMA_SIZE & 0x0FFF) | (0x04 << 12) | (0x04 << 15)
				| (0x02 << 18) | (0x02 << 21) | (1 << 26) | 0x80000000;
		}
		else if ( DMAMode == P2M )
		{
			/* Ch1 set for P2M transfer from MCI_FIFO to memory. */
			DMACC1SrcAddr = DMA_MCIFIFO;
			DMACC1DestAddr = DMA_DST;
			/* The burst size is set to 8, the size is 8 bit too. */
			/* Terminal Count Int enable */
			DMACC1Control = (DMA_SIZE & 0x0FFF) | (0x02 << 12) | (0x02 << 15)
				| (0x02 << 18) | (0x02 << 21) | (1 << 27) | 0x80000000;
		}
		else
		{
			return ( FALSE );
		}
	}
	else
	{
		return ( FALSE );
	}
	
	DMACConfiguration = 0x01;	/* Enable DMA channels, little endian */
	while ( !(DMACConfiguration & 0x01) );    
    return (TRUE);
}

#endif