m32r.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(le:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "register_operand" "")))
   (clobber (reg:CC 17))]
  "optimize_size"
  [(set (reg:CC 17)
	(lt:CC (match_dup 2)
	       (match_dup 1)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_expand "sgt"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_slt_insn (op0, op2, op1));
  DONE;
}")

(define_expand "sge"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sge_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sge_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(ge:SI (match_operand:SI 1 "register_operand" "r,r")
	       (match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:CC 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8,10")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ge:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:CC 17))]
  "!optimize_size"
  [(set (reg:CC 17)
	(lt:CC (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ge:SI (match_operand:SI 1 "register_operand" "")
	       (match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:CC 17))]
  "optimize_size"
  [(set (reg:CC 17)
	(lt:CC (match_dup 1)
	       (match_dup 2)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_expand "sltu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sltu_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sltu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(ltu:SI (match_operand:SI 1 "register_operand" "r,r")
		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:CC 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "6,8")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(ltu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:CC 17))]
  ""
  [(set (reg:CC 17)
	(ltu:CC (match_dup 1)
		(match_dup 2)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))]
  "")

(define_expand "sleu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (GET_CODE (op2) == CONST_INT)
    {
      HOST_WIDE_INT value = INTVAL (op2);
      if (value >= 2147483647)
	{
	  emit_move_insn (op0, const1_rtx);
	  DONE;
	}

      op2 = GEN_INT (value+1);
      if (value < 0 || value >= 32767)
	op2 = force_reg (mode, op2);

      emit_insn (gen_sltu_insn (op0, op1, op2));
      DONE;
    }

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sleu_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sleu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(leu:SI (match_operand:SI 1 "register_operand" "r")
		(match_operand:SI 2 "register_operand" "r")))
   (clobber (reg:CC 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(leu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "register_operand" "")))
   (clobber (reg:CC 17))]
  "!optimize_size"
  [(set (reg:CC 17)
	(ltu:CC (match_dup 2)
		(match_dup 1)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(leu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "register_operand" "")))
   (clobber (reg:CC 17))]
  "optimize_size"
  [(set (reg:CC 17)
	(ltu:CC (match_dup 2)
		(match_dup 1)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_expand "sgtu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! register_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sltu_insn (op0, op2, op1));
  DONE;
}")

(define_expand "sgeu"
  [(match_operand:SI 0 "register_operand" "")]
  ""
  "
{
  rtx op0 = operands[0];
  rtx op1 = m32r_compare_op0;
  rtx op2 = m32r_compare_op1;
  enum machine_mode mode = GET_MODE (op0);

  if (mode != SImode)
    FAIL;

  if (! register_operand (op1, mode))
    op1 = force_reg (mode, op1);

  if (! reg_or_int16_operand (op2, mode))
    op2 = force_reg (mode, op2);

  emit_insn (gen_sgeu_insn (op0, op1, op2));
  DONE;
}")

(define_insn "sgeu_insn"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(geu:SI (match_operand:SI 1 "register_operand" "r,r")
		(match_operand:SI 2 "reg_or_int16_operand" "r,J")))
   (clobber (reg:CC 17))]
  ""
  "#"
  [(set_attr "type" "multi")
   (set_attr "length" "8,10")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(geu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:CC 17))]
  "!optimize_size"
  [(set (reg:CC 17)
	(ltu:CC (match_dup 1)
		(match_dup 2)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(xor:SI (match_dup 0)
		(const_int 1)))]
  "")

;; If optimizing for space, use -(reg - 1) to invert the comparison rather than
;; xor reg,reg,1 which might eliminate a NOP being inserted.
(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(geu:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "reg_or_int16_operand" "")))
   (clobber (reg:CC 17))]
  "optimize_size"
  [(set (reg:CC 17)
	(ltu:CC (match_dup 1)
		(match_dup 2)))
   (set (match_dup 0)
	(ne:SI (reg:CC 17) (const_int 0)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (match_dup 0)
	(neg:SI (match_dup 0)))]
  "")

(define_insn "movcc_insn"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ne:SI (reg:CC 17) (const_int 0)))]
  ""
  "mvfc %0, cbr"
  [(set_attr "type" "misc")
   (set_attr "length" "2")])


;; Unconditional and other jump instructions.

(define_insn "jump"
  [(set (pc) (label_ref (match_operand 0 "" "")))]
  ""
  "bra %l0"
  [(set_attr "type" "uncond_branch")
   (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
						 (const_int 400))
					   (const_int 800))
				      (const_int 2)
				      (const_int 4)))])

(define_insn "indirect_jump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
  ""
  "jmp %a0"
  [(set_attr "type" "uncond_branch")
   (set_attr "length" "2")])

(define_insn "return"
  [(return)]
  "direct_return ()"
  "jmp lr"
  [(set_attr "type" "uncond_branch")
   (set_attr "length" "2")])
 
(define_expand "tablejump"
  [(parallel [(set (pc) (match_operand 0 "register_operand" "r"))
              (use (label_ref (match_operand 1 "" "")))])]
  ""
  "
{
  /* In pic mode, our address differences are against the base of the
     table.  Add that base value back in; CSE ought to be able to combine
     the two address loads.  */
  if (flag_pic)
    {
      rtx tmp, tmp2;

      tmp = gen_rtx_LABEL_REF (Pmode, operands[1]);
      tmp2 = operands[0];
      tmp = gen_rtx_PLUS (Pmode, tmp2, tmp);
      operands[0] = memory_address (Pmode, tmp);
    }
}")

(define_insn "*tablejump_insn"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp %a0"
  [(set_attr "type" "uncond_branch")
   (set_attr "length" "2")])

(define_expand "call"
  ;; operands[1] is stack_size_rtx
  ;; operands[2] is next_arg_register
  [(parallel [(call (match_operand:SI 0 "call_operand" "")
		    (match_operand 1 "" ""))
	     (clobber (reg:SI 14))])]
  ""
  "
{
  if (flag_pic)
    current_function_uses_pic_offset_table = 1;
}")

(define_insn "*call_via_reg"
  [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
	 (match_operand 1 "" ""))
   (clobber (reg:SI 14))]
  ""
  "jl %0"
  [(set_attr "type" "call")
   (set_attr "length" "2")])

(define_insn "*call_via_label"
  [(call (mem:SI (match_operand:SI 0 "call_address_operand" ""))
	 (match_operand 1 "" ""))
   (clobber (reg:SI 14))]
  ""
  "*
{
  int call26_p = call26_operand (operands[0], FUNCTION_MODE);

  if (! call26_p)
    {
      /* We may not be able to reach with a `bl' insn so punt and leave it to
	 the linker.
	 We do this here, rather than doing a force_reg in the define_expand
	 so these insns won't be separated, say by scheduling, thus simplifying
	 the linker.  */
      return \"seth r14,%T0\;add3 r14,r14,%B0\;jl r14\";
    }
  else
    return \"bl %0\";
}"
  [(set_attr "type" "call")
   (set (attr "length")
	(if_then_else (eq (symbol_ref "call26_operand (operands[0], FUNCTION_MODE)")
			  (const_int 0))
		      (const_int 12) ; 10 + 2 for nop filler
		      ; The return address must be on a 4 byte boundary so
		      ; there's no point in using a value of 2 here.  A 2 byte
		      ; insn may go in the left slot but we currently can't
		      ; use such knowledge.
		      (const_int 4)))])

(define_expand "call_value"
  ;; operand 2 is stack_size_rtx
  ;; operand 3 is next_arg_register
  [(parallel [(set (match_operand 0 "register_operand" "=r")
		   (call (match_operand:SI 1 "call_operand" "")
			 (match_operand 2 "" "")))
	     (clobber (reg:SI 14))])]
  ""
  "                                                                             
{
  if (flag_pic)
    current_function_uses_pic_offset_table