ppro.md

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;; Scheduling for the Intel P6 family of processors
;; Copyright (C) 2004, 2005 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.  */

;; The P6 family includes the Pentium Pro, Pentium II, Pentium III, Celeron
;; and Xeon lines of CPUs.  The DFA scheduler description in this file is
;; based on information that can be found in the following three documents:
;;
;;    "P6 Family of Processors Hardware Developer's Manual",
;;    Intel, September 1999.
;;
;;    "Intel Architecture Optimization Manual",
;;    Intel, 1999 (Order Number: 245127-001).
;;
;;    "How to optimize for the Pentium family of microprocessors",
;;    by Agner Fog, PhD.
;;
;; The P6 pipeline has three major components:
;;   1) the FETCH/DECODE unit, an in-order issue front-end
;;   2) the DISPATCH/EXECUTE unit, which is the out-of-order core
;;   3) the RETIRE unit, an in-order retirement unit
;;
;; So, the P6 CPUs have out-of-order cores, but the instruction decoder and
;; retirement unit are naturally in-order.
;;
;;                       BUS INTERFACE UNIT
;;                     /                   \
;;                L1 ICACHE             L1 DCACHE
;;              /     |     \              |     \
;;       DECODER0  DECODER1  DECODER2  DISP/EXEC  RETIRE
;;              \     |     /              |        |
;;            INSTRUCTION POOL   __________|_______/
;;          (inc. reorder buffer)
;;
;; Since the P6 CPUs execute instructions out-of-order, the most important
;; consideration in performance tuning is making sure enough micro-ops are
;; ready for execution in the out-of-order core, while not stalling the
;; decoder.
;;
;; TODO:
;; - Find a less crude way to model complex instructions, in
;;   particular how many cycles they take to be decoded.
;; - Include decoder latencies in the total reservation latencies.
;;   This isn't necessary right now because we assume for every
;;   instruction that it never blocks a decoder.
;; - Figure out where the p0 and p1 reservations come from.  These
;;   appear not to be in the manual (e.g. why is cld "(p0+p1)*2"
;;   better than "(p0|p1)*4" ???)
;; - Lots more because I'm sure this is still far from optimal :-)

;; The ppro_idiv and ppro_fdiv automata are used to model issue
;; latencies of idiv and fdiv type insns.
(define_automaton "ppro_decoder,ppro_core,ppro_idiv,ppro_fdiv,ppro_load,ppro_store")

;; Simple instructions of the register-register form have only one uop.
;; Load instructions are also only one uop.  Store instructions decode to
;; two uops, and simple read-modify instructions also take two uops.
;; Simple instructions of the register-memory form have two to three uops.
;; Simple read-modify-write instructions have four uops.  The rules for
;; the decoder are simple:
;;  - an instruction with 1 uop can be decoded by any of the three
;;    decoders in one cycle.
;;  - an instruction with 1 to 4 uops can be decoded only by decoder 0
;;    but still in only one cycle.
;;  - a complex (microcode) instruction can also only be decoded by
;;    decoder 0, and this takes an unspecified number of cycles.
;;    
;; The goal is to schedule such that we have a few-one-one uops sequence
;; in each cycle, to decode as many instructions per cycle as possible.
(define_cpu_unit "decoder0" "ppro_decoder")
(define_cpu_unit "decoder1" "ppro_decoder")
(define_cpu_unit "decoder2" "ppro_decoder")

;; We first wish to find an instruction for decoder0, so exclude
;; decoder1 and decoder2 from being reserved until decoder 0 is
;; reserved.
(presence_set "decoder1" "decoder0")
(presence_set "decoder2" "decoder0")

;; Most instructions can be decoded on any of the three decoders.
(define_reservation "decodern" "(decoder0|decoder1|decoder2)")

;; The out-of-order core has five pipelines.  During each cycle, the core
;; may dispatch zero or one uop on the port of any of the five pipelines
;; so the maximum number of dispatched uops per cycle is 5.  In practicer,
;; 3 uops per cycle is more realistic.
;;
;; Two of the five pipelines contain several execution units:
;;
;; Port 0	Port 1		Port 2		Port 3		Port 4
;; ALU		ALU		LOAD		SAC		SDA
;; FPU		JUE
;; AGU		MMX
;; MMX		P3FPU
;; P3FPU
;;
;; (SAC=Store Address Calculation, SDA=Store Data Unit, P3FPU = SSE unit,
;;  JUE = Jump Execution Unit, AGU = Address Generation Unit)
;;
(define_cpu_unit "p0,p1" "ppro_core")
(define_cpu_unit "p2" "ppro_load")
(define_cpu_unit "p3,p4" "ppro_store")
(define_cpu_unit "idiv" "ppro_idiv")
(define_cpu_unit "fdiv" "ppro_fdiv")

;; Only the irregular instructions have to be modeled here.  A load
;; increases the latency by 2 or 3, or by nothing if the manual gives
;; a latency already.  Store latencies are not accounted for.
;;
;; The simple instructions follow a very regular pattern of 1 uop per
;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
;; on port 4 and port 3.  These instructions are modelled at the bottom
;; of this file.
;;
;; For microcoded instructions we don't know how many uops are produced.
;; These instructions are the "complex" ones in the Intel manuals.  All
;; we _do_ know is that they typically produce four or more uops, so
;; they can only be decoded on decoder0.  Modelling their latencies
;; doesn't make sense because we don't know how these instructions are
;; executed in the core.  So we just model that they can only be decoded
;; on decoder 0, and say that it takes a little while before the result
;; is available.
; APPLE LOCAL begin mainline 2006-04-19 4434601
(define_insn_reservation "ppro_complex_insn" 6
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (eq_attr "type" "other,multi,call,callv,str"))
			 "decoder0")

;; imov with memory operands does not use the integer units.
(define_insn_reservation "ppro_imov" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "imov")))
			 "decodern,(p0|p1)")

(define_insn_reservation "ppro_imov_load" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (eq_attr "type" "imov")))
			 "decodern,p2")

(define_insn_reservation "ppro_imov_store" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "store")
				   (eq_attr "type" "imov")))
			 "decoder0,p4+p3")

;; imovx always decodes to one uop, and also doesn't use the integer
;; units if it has memory operands.
(define_insn_reservation "ppro_imovx" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "imovx")))
			 "decodern,(p0|p1)")

(define_insn_reservation "ppro_imovx_load" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (eq_attr "type" "imovx")))
			 "decodern,p2")

;; lea executes on port 0 with latency one and throughput 1.
(define_insn_reservation "ppro_lea" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "lea")))
			 "decodern,p0")

;; Shift and rotate execute on port 0 with latency and throughput 1.
;; The load and store units need to be reserved when memory operands
;; are involved.
(define_insn_reservation "ppro_shift_rotate" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
			 "decodern,p0")

(define_insn_reservation "ppro_shift_rotate_mem" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "!none")
				   (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
			 "decoder0,p2+p0,p4+p3")

(define_insn_reservation "ppro_cld" 2
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (eq_attr "type" "cld"))
			 "decoder0,(p0+p1)*2")

;; The P6 has a sophisticated branch prediction mechanism to minimize
;; latencies due to branching.  In particular, it has a fast way to
;; execute branches that are taken multiple times (such as in loops).
;; Branches not taken suffer no penalty, and correctly predicted
;; branches cost only one fetch cycle.  Mispredicted branches are very
;; costly: typically 15 cycles and possibly as many as 26 cycles.
;;
;; Unfortunately all this makes it quite difficult to properly model
;; the latencies for the compiler.  Here I've made the choice to be
;; optimistic and assume branches are often predicted correctly, so
;; they have latency 1, and the decoders are not blocked.
;;
;; In addition, the model assumes a branch always decodes to only 1 uop,
;; which is not exactly true because there are a few instructions that
;; decode to 2 uops or microcode.  But this probably gives the best
;; results because we can assume these instructions can decode on all
;; decoders.
(define_insn_reservation "ppro_branch" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "ibr")))
			 "decodern,p1")

;; ??? Indirect branches probably have worse latency than this.
(define_insn_reservation "ppro_indirect_branch" 6
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "!none")
				   (eq_attr "type" "ibr")))
			 "decoder0,p2+p1")

(define_insn_reservation "ppro_leave" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (eq_attr "type" "leave"))
			 "decoder0,p2+(p0|p1),(p0|p1)")

;; imul has throughput one, but latency 4, and can only execute on port 0.
(define_insn_reservation "ppro_imul" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "imul")))
			 "decodern,p0")

(define_insn_reservation "ppro_imul_mem" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "!none")
				   (eq_attr "type" "imul")))
			 "decoder0,p2+p0")

;; div and idiv are very similar, so we model them the same.
;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
;; These issue latencies are modelled via the ppro_div automaton.
(define_insn_reservation "ppro_idiv_QI" 19
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (and (eq_attr "mode" "QI")
					(eq_attr "type" "idiv"))))
			 "decoder0,(p0+idiv)*2,(p0|p1)+idiv,idiv*9")

(define_insn_reservation "ppro_idiv_QI_load" 19
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (and (eq_attr "mode" "QI")
					(eq_attr "type" "idiv"))))
			 "decoder0,p2+p0+idiv,p0+idiv,(p0|p1)+idiv,idiv*9")

(define_insn_reservation "ppro_idiv_HI" 23
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (and (eq_attr "mode" "HI")
					(eq_attr "type" "idiv"))))
			 "decoder0,(p0+idiv)*3,(p0|p1)+idiv,idiv*17")

(define_insn_reservation "ppro_idiv_HI_load" 23
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (and (eq_attr "mode" "HI")
					(eq_attr "type" "idiv"))))
			 "decoder0,p2+p0+idiv,p0+idiv,(p0|p1)+idiv,idiv*18")

(define_insn_reservation "ppro_idiv_SI" 39
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (and (eq_attr "mode" "SI")
					(eq_attr "type" "idiv"))))
			 "decoder0,(p0+idiv)*3,(p0|p1)+idiv,idiv*33")

(define_insn_reservation "ppro_idiv_SI_load" 39
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (and (eq_attr "mode" "SI")
					(eq_attr "type" "idiv"))))
			 "decoder0,p2+p0+idiv,p0+idiv,(p0|p1)+idiv,idiv*34")

;; Floating point operations always execute on port 0.
;; ??? where do these latencies come from? fadd has latency 3 and
;;     has throughput "1/cycle (align with FADD)".  What do they
;;     mean and how can we model that?
(define_insn_reservation "ppro_fop" 3
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none,unknown")
				   (eq_attr "type" "fop")))
			 "decodern,p0")

(define_insn_reservation "ppro_fop_load" 5
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (eq_attr "type" "fop")))
			 "decoder0,p2+p0,p0")

(define_insn_reservation "ppro_fop_store" 3
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "store")
				   (eq_attr "type" "fop")))
			 "decoder0,p0,p0,p0+p4+p3")

(define_insn_reservation "ppro_fop_both" 5
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "both")
				   (eq_attr "type" "fop")))
			 "decoder0,p2+p0,p0+p4+p3")

(define_insn_reservation "ppro_fsgn" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (eq_attr "type" "fsgn"))
			 "decodern,p0")

(define_insn_reservation "ppro_fistp" 5
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (eq_attr "type" "fistp"))
			 "decoder0,p0*2,p4+p3")

(define_insn_reservation "ppro_fcmov" 2
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (eq_attr "type" "fcmov"))
			 "decoder0,p0*2")

(define_insn_reservation "ppro_fcmp" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "fcmp")))
			 "decodern,p0")

(define_insn_reservation "ppro_fcmp_load" 4
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (eq_attr "type" "fcmp")))
			 "decoder0,p2+p0")

(define_insn_reservation "ppro_fmov" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "none")
				   (eq_attr "type" "fmov")))
			 "decodern,p0")

(define_insn_reservation "ppro_fmov_load" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (and (eq_attr "mode" "!XF")
					(eq_attr "type" "fmov"))))
			 "decodern,p2")

(define_insn_reservation "ppro_fmov_XF_load" 3
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "load")
				   (and (eq_attr "mode" "XF")
					(eq_attr "type" "fmov"))))
			 "decoder0,(p2+p0)*2")

(define_insn_reservation "ppro_fmov_store" 1
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "store")
				   (and (eq_attr "mode" "!XF")
					(eq_attr "type" "fmov"))))
			 "decodern,p0")

(define_insn_reservation "ppro_fmov_XF_store" 3
			 (and (eq_attr "cpu" "pentiumpro,generic32")
			      (and (eq_attr "memory" "store")
				   (and (eq_attr "mode" "XF")