athlon.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

			 (and (eq_attr "cpu" "k8,generic64")
			      (eq_attr "type" "sselog,sselog1"))
			 "athlon-double,athlon-fpsched,athlon-fmul")
;; ??? pcmp executes in addmul, probably not worthwhile to bother about that.
(define_insn_reservation "athlon_ssecmp_load" 2
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "mode" "SF,DF,DI")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_ssecmp_load_k8" 4
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssecmp")
				   (and (eq_attr "mode" "SF,DF,DI,TI")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_ssecmp" 2
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssecmp")
				   (eq_attr "mode" "SF,DF,DI,TI")))
			 "athlon-direct,athlon-fpsched,athlon-fadd")
(define_insn_reservation "athlon_ssecmpvector_load" 3
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssecmp")
				   (eq_attr "memory" "load")))
			 "athlon-vector,athlon-fpload2,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecmpvector_load_k8" 5
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssecmp")
				   (eq_attr "memory" "load")))
			 "athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecmpvector" 3
			 (and (eq_attr "cpu" "athlon")
			      (eq_attr "type" "ssecmp"))
			 "athlon-vector,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecmpvector_k8" 3
			 (and (eq_attr "cpu" "k8,generic64")
			      (eq_attr "type" "ssecmp"))
			 "athlon-double,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecomi_load" 4
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssecomi")
				   (eq_attr "memory" "load")))
			 "athlon-vector,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_ssecomi_load_k8" 6
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssecomi")
				   (eq_attr "memory" "load")))
			 "athlon-vector,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_ssecomi" 4
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (eq_attr "type" "ssecmp"))
			 "athlon-vector,athlon-fpsched,athlon-fadd")
(define_insn_reservation "athlon_sseadd_load" 4
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "sseadd")
				   (and (eq_attr "mode" "SF,DF,DI")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_sseadd_load_k8" 6
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "sseadd")
				   (and (eq_attr "mode" "SF,DF,DI")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_sseadd" 4
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "sseadd")
				   (eq_attr "mode" "SF,DF,DI")))
			 "athlon-direct,athlon-fpsched,athlon-fadd")
(define_insn_reservation "athlon_sseaddvector_load" 5
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "sseadd")
				   (eq_attr "memory" "load")))
			 "athlon-vector,athlon-fpload2,(athlon-fadd*2)")
(define_insn_reservation "athlon_sseaddvector_load_k8" 7
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "sseadd")
				   (eq_attr "memory" "load")))
			 "athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
(define_insn_reservation "athlon_sseaddvector" 5
			 (and (eq_attr "cpu" "athlon")
			      (eq_attr "type" "sseadd"))
			 "athlon-vector,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_sseaddvector_k8" 5
			 (and (eq_attr "cpu" "k8,generic64")
			      (eq_attr "type" "sseadd"))
			 "athlon-double,athlon-fpsched,(athlon-fadd*2)")

;; Conversions behaves very irregularly and the scheduling is critical here.
;; Take each instruction separately.  Assume that the mode is always set to the
;; destination one and athlon_decode is set to the K8 versions.

;; cvtss2sd
(define_insn_reservation "athlon_ssecvt_cvtss2sd_load_k8" 4
			 (and (eq_attr "cpu" "k8,athlon,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "direct")
					(and (eq_attr "mode" "DF")
					     (eq_attr "memory" "load")))))
			 "athlon-direct,athlon-fploadk8,athlon-fstore")
(define_insn_reservation "athlon_ssecvt_cvtss2sd" 2
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "direct")
					(eq_attr "mode" "DF"))))
			 "athlon-direct,athlon-fpsched,athlon-fstore")
;; cvtps2pd.  Model same way the other double decoded FP conversions.
(define_insn_reservation "athlon_ssecvt_cvtps2pd_load_k8" 5
			 (and (eq_attr "cpu" "k8,athlon,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "V2DF,V4SF,TI")
					     (eq_attr "memory" "load")))))
			 "athlon-double,athlon-fpload2k8,(athlon-fstore*2)")
(define_insn_reservation "athlon_ssecvt_cvtps2pd_k8" 3
			 (and (eq_attr "cpu" "k8,athlon,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "double")
					(eq_attr "mode" "V2DF,V4SF,TI"))))
			 "athlon-double,athlon-fpsched,athlon-fstore,athlon-fstore")
;; cvtsi2sd mem,reg is directpath path  (cvtsi2sd reg,reg is doublepath)
;; cvtsi2sd has troughput 1 and is executed in store unit with latency of 6
(define_insn_reservation "athlon_sseicvt_cvtsi2sd_load" 6
			 (and (eq_attr "cpu" "athlon,k8")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "direct")
					(and (eq_attr "mode" "SF,DF")
					     (eq_attr "memory" "load")))))
			 "athlon-direct,athlon-fploadk8,athlon-fstore")
;; cvtsi2ss mem, reg is doublepath
(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load" 9
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "SF,DF")
					     (eq_attr "memory" "load")))))
			 "athlon-vector,athlon-fpload,(athlon-fstore*2)")
(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load_k8" 9
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "SF,DF")
					     (eq_attr "memory" "load")))))
			 "athlon-double,athlon-fploadk8,(athlon-fstore*2)")
;; cvtsi2sd reg,reg is double decoded (vector on Athlon)
(define_insn_reservation "athlon_sseicvt_cvtsi2sd_k8" 11
			 (and (eq_attr "cpu" "k8,athlon,generic64")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "SF,DF")
					     (eq_attr "memory" "none")))))
			 "athlon-double,athlon-fploadk8,athlon-fstore")
;; cvtsi2ss reg, reg is doublepath
(define_insn_reservation "athlon_sseicvt_cvtsi2ss" 14
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "vector")
					(and (eq_attr "mode" "SF,DF")
					     (eq_attr "memory" "none")))))
			 "athlon-vector,athlon-fploadk8,(athlon-fvector*2)")
;; cvtsd2ss mem,reg is doublepath, troughput unknown, latency 9
(define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_k8" 9
			 (and (eq_attr "cpu" "k8,athlon,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "SF")
					     (eq_attr "memory" "load")))))
			 "athlon-double,athlon-fploadk8,(athlon-fstore*3)")
;; cvtsd2ss reg,reg is vectorpath, troughput unknown, latency 12
(define_insn_reservation "athlon_ssecvt_cvtsd2ss" 12
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "vector")
					(and (eq_attr "mode" "SF")
					     (eq_attr "memory" "none")))))
			 "athlon-vector,athlon-fpsched,(athlon-fvector*3)")
(define_insn_reservation "athlon_ssecvt_cvtpd2ps_load_k8" 8
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "vector")
					(and (eq_attr "mode" "V4SF,V2DF,TI")
					     (eq_attr "memory" "load")))))
			 "athlon-double,athlon-fpload2k8,(athlon-fstore*3)")
;; cvtpd2ps mem,reg is vectorpath, troughput unknown, latency 10
;; ??? Why it is fater than cvtsd2ss?
(define_insn_reservation "athlon_ssecvt_cvtpd2ps" 8
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssecvt")
				   (and (eq_attr "athlon_decode" "vector")
					(and (eq_attr "mode" "V4SF,V2DF,TI")
					     (eq_attr "memory" "none")))))
			 "athlon-vector,athlon-fpsched,athlon-fvector*2")
;; cvtsd2si mem,reg is doublepath, troughput 1, latency 9
(define_insn_reservation "athlon_secvt_cvtsX2si_load" 9
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "vector")
					(and (eq_attr "mode" "SI,DI")
					     (eq_attr "memory" "load")))))
			 "athlon-vector,athlon-fploadk8,athlon-fvector")
;; cvtsd2si reg,reg is doublepath, troughput 1, latency 9
(define_insn_reservation "athlon_ssecvt_cvtsX2si" 9
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "SI,DI")
					     (eq_attr "memory" "none")))))
			 "athlon-vector,athlon-fpsched,athlon-fvector")
(define_insn_reservation "athlon_ssecvt_cvtsX2si_k8" 9
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "sseicvt")
				   (and (eq_attr "athlon_decode" "double")
					(and (eq_attr "mode" "SI,DI")
					     (eq_attr "memory" "none")))))
			 "athlon-double,athlon-fpsched,athlon-fstore")


(define_insn_reservation "athlon_ssemul_load" 4
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssemul")
				   (and (eq_attr "mode" "SF,DF")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fpload,athlon-fmul")
(define_insn_reservation "athlon_ssemul_load_k8" 6
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssemul")
				   (and (eq_attr "mode" "SF,DF")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fploadk8,athlon-fmul")
(define_insn_reservation "athlon_ssemul" 4
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "mode" "SF,DF")))
			 "athlon-direct,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_ssemulvector_load" 5
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "memory" "load")))
			 "athlon-vector,athlon-fpload2,(athlon-fmul*2)")
(define_insn_reservation "athlon_ssemulvector_load_k8" 7
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssemul")
				   (eq_attr "memory" "load")))
			 "athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
(define_insn_reservation "athlon_ssemulvector" 5
			 (and (eq_attr "cpu" "athlon")
			      (eq_attr "type" "ssemul"))
			 "athlon-vector,athlon-fpsched,(athlon-fmul*2)")
(define_insn_reservation "athlon_ssemulvector_k8" 5
			 (and (eq_attr "cpu" "k8,generic64")
			      (eq_attr "type" "ssemul"))
			 "athlon-double,athlon-fpsched,(athlon-fmul*2)")
;; divsd timings.  divss is faster
(define_insn_reservation "athlon_ssediv_load" 20
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "SF,DF")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fpload,athlon-fmul*17")
(define_insn_reservation "athlon_ssediv_load_k8" 22
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssediv")
				   (and (eq_attr "mode" "SF,DF")
					(eq_attr "memory" "load"))))
			 "athlon-direct,athlon-fploadk8,athlon-fmul*17")
(define_insn_reservation "athlon_ssediv" 20
			 (and (eq_attr "cpu" "athlon,k8,generic64")
			      (and (eq_attr "type" "ssediv")
				   (eq_attr "mode" "SF,DF")))
			 "athlon-direct,athlon-fpsched,athlon-fmul*17")
(define_insn_reservation "athlon_ssedivvector_load" 39
			 (and (eq_attr "cpu" "athlon")
			      (and (eq_attr "type" "ssediv")
				   (eq_attr "memory" "load")))
			 "athlon-vector,athlon-fpload2,athlon-fmul*34")
(define_insn_reservation "athlon_ssedivvector_load_k8" 35
			 (and (eq_attr "cpu" "k8,generic64")
			      (and (eq_attr "type" "ssediv")
				   (eq_attr "memory" "load")))
			 "athlon-double,athlon-fpload2k8,athlon-fmul*34")
(define_insn_reservation "athlon_ssedivvector" 39
			 (and (eq_attr "cpu" "athlon")
			      (eq_attr "type" "ssediv"))
			 "athlon-vector,athlon-fmul*34")
(define_insn_reservation "athlon_ssedivvector_k8" 39
			 (and (eq_attr "cpu" "k8,generic64")
			      (eq_attr "type" "ssediv"))
			 "athlon-double,athlon-fmul*34")
; APPLE LOCAL end mainline 2006-04-19 4434601