📄 c4x.md
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(if_then_else (and (match_operand 0 "reg_imm_operand" "") (and (match_operand 1 "reg_imm_operand" "") (match_operand 2 "reg_imm_operand" ""))) (const_string "true") (const_string "false"))] (const_string "false")))(define_attr "onlyreg_nomod" "false,true" (cond [(eq_attr "type" "unary,unarycc,compare,lda,store") (if_then_else (and (match_operand 0 "not_modify_reg" "") (match_operand 1 "not_modify_reg" "")) (const_string "true") (const_string "false")) (eq_attr "type" "binary,binarycc") (if_then_else (and (match_operand 0 "not_modify_reg" "") (and (match_operand 1 "not_modify_reg" "") (match_operand 2 "not_modify_reg" ""))) (const_string "true") (const_string "false"))] (const_string "false")))(define_attr "not_repeat_reg" "false,true" (cond [(eq_attr "type" "unary,unarycc,compare,lda,ldp,store") (if_then_else (and (match_operand 0 "not_rc_reg" "") (match_operand 1 "not_rc_reg" "")) (const_string "true") (const_string "false")) (eq_attr "type" "binary,binarycc") (if_then_else (and (match_operand 0 "not_rc_reg" "") (and (match_operand 1 "not_rc_reg" "") (match_operand 2 "not_rc_reg" ""))) (const_string "true") (const_string "false"))] (const_string "false")))/* Disable compare because the c4x contains a bug. The cmpi insn sets the CC in the read phase of the pipeline instead of the execution phase when two registers are compared. */(define_attr "in_annul_slot_1" "false,true" (if_then_else (and (and (eq_attr "cpu" "c4x") (eq_attr "type" "!jump,call,rets,jmpc,compare,db,dbc,repeat,repeat_top,laj,push,pop,lda,ldp,multi")) (eq_attr "onlyreg" "true")) (const_string "true") (const_string "false")))(define_attr "in_annul_slot_2" "false,true" (if_then_else (and (and (eq_attr "cpu" "c4x") (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi")) (eq_attr "onlyreg_nomod" "true")) (const_string "true") (const_string "false")))/* Disable ldp because the c4x contains a bug. The ldp insn modifies the dp register when the insn is anulled or not. Also disable autoincrement insns because of a silicon bug. */(define_attr "in_annul_slot_3" "false,true" (if_then_else (and (and (eq_attr "cpu" "c4x") (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,ldp,multi")) (eq_attr "onlyreg_nomod" "true")) (const_string "true") (const_string "false")))(define_attr "in_delay_slot" "false,true" (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi") (const_string "true") (const_string "false")))(define_attr "in_repeat_slot" "false,true" (if_then_else (and (eq_attr "cpu" "c4x") (and (eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,multi") (eq_attr "not_repeat_reg" "true"))) (const_string "true") (const_string "false")))(define_attr "in_dbc_slot" "false,true" (if_then_else (eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,compare,db,dbc,repeat,repeat_top,laj,multi") (const_string "true") (const_string "false")))(define_delay (eq_attr "type" "jmpc") [(eq_attr "in_delay_slot" "true") (eq_attr "in_annul_slot_1" "true") (eq_attr "in_annul_slot_1" "true") (eq_attr "in_delay_slot" "true") (eq_attr "in_annul_slot_2" "true") (eq_attr "in_annul_slot_2" "true") (eq_attr "in_delay_slot" "true") (eq_attr "in_annul_slot_3" "true") (eq_attr "in_annul_slot_3" "true") ])(define_delay (eq_attr "type" "repeat_top") [(eq_attr "in_repeat_slot" "true") (nil) (nil) (eq_attr "in_repeat_slot" "true") (nil) (nil) (eq_attr "in_repeat_slot" "true") (nil) (nil)])(define_delay (eq_attr "type" "jump,db") [(eq_attr "in_delay_slot" "true") (nil) (nil) (eq_attr "in_delay_slot" "true") (nil) (nil) (eq_attr "in_delay_slot" "true") (nil) (nil)]); Decrement and branch conditional instructions cannot modify the; condition codes for the cycles in the delay slots.;(define_delay (eq_attr "type" "dbc") [(eq_attr "in_dbc_slot" "true") (nil) (nil) (eq_attr "in_dbc_slot" "true") (nil) (nil) (eq_attr "in_dbc_slot" "true") (nil) (nil)]); The LAJ instruction has three delay slots but the last slot is; used for pushing the return address. Thus we can only use two slots.;(define_delay (eq_attr "type" "laj") [(eq_attr "in_delay_slot" "true") (nil) (nil) (eq_attr "in_delay_slot" "true") (nil) (nil)]);; C4x UNSPEC NUMBERS;(define_constants [ (UNSPEC_BU 1) (UNSPEC_RPTS 2) (UNSPEC_LSH 3) (UNSPEC_CMPHI 4) (UNSPEC_RCPF 5) (UNSPEC_RND 6) (UNSPEC_RPTB_FILL 7) (UNSPEC_LOADHF_INT 8) (UNSPEC_STOREHF_INT 9) (UNSPEC_RSQRF 10) (UNSPEC_LOADQF_INT 11) (UNSPEC_STOREQF_INT 12) (UNSPEC_LDIV 13) (UNSPEC_PUSH_ST 14) (UNSPEC_POP_ST 15) (UNSPEC_PUSH_DP 16) (UNSPEC_POP_DP 17) (UNSPEC_POPQI 18) (UNSPEC_POPQF 19) (UNSPEC_ANDN_ST 20) (UNSPEC_RPTB_INIT 22) (UNSPEC_TOIEEE 23) (UNSPEC_FRIEEE 24) ]);; C4x PIPELINE MODEL;; With the C3x, an external memory write (with no wait states) takes; two cycles and an external memory read (with no wait states) takes; one cycle. However, an external read following an external write; takes two cycles. With internal memory, reads and writes take; half a cycle.; When a C4x address register is loaded it will not be available for; an extra machine cycle. Calculating with a C4x address register; makes it unavailable for 2 machine cycles.;; Just some dummy definitions. The real work is done in c4x_adjust_cost.; These are needed so the min/max READY_DELAY is known.(define_insn_reservation "any_insn" 1 (const_int 1) "nothing")(define_insn_reservation "slowest_insn" 3 (const_int 0) "nothing"); The attribute setar0 is set to 1 for insns where ar0 is a dst operand.; Note that the attributes unarycc and binarycc do not apply; if ar0 is a dst operand (only loading an ext. prec. reg. sets CC)(define_attr "setar0" "" (cond [(eq_attr "type" "unary,binary") (if_then_else (match_operand 0 "ar0_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setlda_ar0" "" (cond [(eq_attr "type" "lda") (if_then_else (match_operand 0 "ar0_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0))); The attribute usear0 is set to 1 for insns where ar0 is used; for addressing, as a src operand, or as a dst operand.(define_attr "usear0" "" (cond [(eq_attr "type" "compare,store") (if_then_else (match_operand 0 "ar0_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar0_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar0_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "db,dbc") (if_then_else (match_operand 0 "ar0_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0))); The attribute readar0 is set to 1 for insns where ar0 is a src operand.(define_attr "readar0" "" (cond [(eq_attr "type" "compare") (if_then_else (match_operand 0 "ar0_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar0_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar0_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setar1" "" (cond [(eq_attr "type" "unary,binary") (if_then_else (match_operand 0 "ar1_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setlda_ar1" "" (cond [(eq_attr "type" "lda") (if_then_else (match_operand 0 "ar1_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "usear1" "" (cond [(eq_attr "type" "compare,store") (if_then_else (match_operand 0 "ar1_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar1_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar1_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "db,dbc") (if_then_else (match_operand 0 "ar1_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "readar1" "" (cond [(eq_attr "type" "compare") (if_then_else (match_operand 0 "ar1_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar1_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar1_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setar2" "" (cond [(eq_attr "type" "unary,binary") (if_then_else (match_operand 0 "ar2_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setlda_ar2" "" (cond [(eq_attr "type" "lda") (if_then_else (match_operand 0 "ar2_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "usear2" "" (cond [(eq_attr "type" "compare,store") (if_then_else (match_operand 0 "ar2_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar2_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar2_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "db,dbc") (if_then_else (match_operand 0 "ar2_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "readar2" "" (cond [(eq_attr "type" "compare") (if_then_else (match_operand 0 "ar2_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar2_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar2_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setar3" "" (cond [(eq_attr "type" "unary,binary") (if_then_else (match_operand 0 "ar3_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setlda_ar3" "" (cond [(eq_attr "type" "lda") (if_then_else (match_operand 0 "ar3_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "usear3" "" (cond [(eq_attr "type" "compare,store") (if_then_else (match_operand 0 "ar3_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar3_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar3_mem_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "db,dbc") (if_then_else (match_operand 0 "ar3_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "readar3" "" (cond [(eq_attr "type" "compare") (if_then_else (match_operand 0 "ar3_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "compare,store,lda,unary,unarycc,binary,binarycc") (if_then_else (match_operand 1 "ar3_reg_operand" "") (const_int 1) (const_int 0)) (eq_attr "type" "binary,binarycc") (if_then_else (match_operand 2 "ar3_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setar4" "" (cond [(eq_attr "type" "unary,binary") (if_then_else (match_operand 0 "ar4_reg_operand" "") (const_int 1) (const_int 0))] (const_int 0)))(define_attr "setlda_ar4" ""
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