stormy16.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

  ""
  "mul"
  [(set_attr "psw_operand" "nop")])

;; Unsigned division giving both quotient and remainder
(define_insn "udivmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(udiv:HI (match_operand:HI 1 "register_operand" "a")
		 (match_operand:HI 2 "register_operand" "c")))
   (set (match_operand:HI 3 "register_operand" "=b")
	(umod:HI (match_dup 1)
		 (match_dup 2)))]
  ""
  "div"
  [(set_attr "psw_operand" "nop")])

;; Signed division giving both quotient and remainder
(define_insn "divmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(div:HI (match_operand:HI 1 "register_operand" "a")
		 (match_operand:HI 2 "register_operand" "c")))
   (set (match_operand:HI 3 "register_operand" "=b")
	(mod:HI (match_dup 1)
		 (match_dup 2)))]
  ""
  "sdiv"
  [(set_attr "psw_operand" "nop")])

;; Signed 32/16 division
(define_insn "sdivlh"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(div:HI (match_operand:SI 2 "register_operand" "t")
		 (match_operand:HI 3 "register_operand" "c")))
   (set (match_operand:HI 1 "register_operand" "=b")
	(mod:HI (match_dup 2)
		 (match_dup 3)))]
  ""
  "sdivlh"
  [(set_attr "psw_operand" "nop")])

;; Unsigned 32/16 division
(define_insn "udivlh"
  [(set (match_operand:HI 0 "register_operand" "=a")
	(udiv:HI (match_operand:SI 2 "register_operand" "t")
		 (match_operand:HI 3 "register_operand" "c")))
   (set (match_operand:HI 1 "register_operand" "=b")
	(umod:HI (match_dup 2)
		 (match_dup 3)))]
  ""
  "divlh"
  [(set_attr "psw_operand" "nop")])

;; Negation

(define_expand "neghi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(not:HI (match_operand:HI 1 "register_operand" "")))
   (parallel [(set (match_dup 0) (plus:HI (match_dup 0) (const_int 1)))
	      (clobber (match_scratch:BI 3 ""))])]
  ""
  "")


;; ::::::::::::::::::::
;; ::
;; :: 16 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::

;; Arithmetic Shift Left
(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashift:HI (match_operand:HI 1 "register_operand" "0")
		   (match_operand:HI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "shl %0,%2")

;; Arithmetic Shift Right
(define_insn "ashrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:HI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "asr %0,%2")

;; Logical Shift Right
(define_insn "lshrhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
		     (match_operand:HI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "shr %0,%2")


;; ::::::::::::::::::::
;; ::
;; :: 16 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::

;; Logical AND, 16 bit integers
(define_insn "andhi3"
  [(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
	(and:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "L,r,K,i,K")))]
  ""
  "@
   and Rx,%2
   and %0,%2
   clr1 %0,%B2
   and %0,%2
   #"
  [(set_attr "length" "2,2,2,4,2")])

(define_split
  [(set (match_operand:HI 0 "xstormy16_below100_operand" "")
	(and:HI (match_operand:HI 1 "xstormy16_below100_operand" "")
		(match_operand:HI 2 "xstormy16_onebit_clr_operand" "")))]
  ""
  [(set (match_dup 3)
	(and:QI (match_dup 4)
		(match_dup 5)))]
  "{ int s = ((INTVAL (operands[2]) & 0xff) == 0xff) ? 1 : 0;
     operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s);
     operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s);
     operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s);
     operands[5] = GEN_INT (INTVAL (operands[5]) | ~(HOST_WIDE_INT)0xff);
   }
")

;; Inclusive OR, 16 bit integers
(define_insn "iorhi3"
  [(set (match_operand:HI 0 "xstormy16_splittable_below100_or_register" "=T,r,r,r,W")
	(ior:HI (match_operand:HI 1 "xstormy16_below100_or_register" "%0,0,0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "L,r,J,i,J")))]
  ""
  "@
   or Rx,%2
   or %0,%2
   set1 %0,%B2
   or %0,%2
   #"
  [(set_attr "length" "2,2,2,4,2")])

(define_split
  [(set (match_operand:HI 0 "xstormy16_below100_operand" "")
	(ior:HI (match_operand:HI 1 "xstormy16_below100_operand" "")
		(match_operand:HI 2 "xstormy16_onebit_set_operand" "")))]
  ""
  [(set (match_dup 3)
	(ior:QI (match_dup 4)
		(match_dup 5)))]
  "{ int s = ((INTVAL (operands[2]) & 0xff) == 0x00) ? 1 : 0;
     operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, s);
     operands[4] = simplify_gen_subreg (QImode, operands[1], HImode, s);
     operands[5] = simplify_gen_subreg (QImode, operands[2], HImode, s);
     operands[5] = GEN_INT (INTVAL (operands[5]) & 0xff);
   }
")

;; Exclusive OR, 16 bit integers
(define_insn "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "=T,r,r")
	(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "L,r,i")))]
  ""
  "@
   xor Rx,%2
   xor %0,%2
   xor %0,%2"
  [(set_attr "length" "2,2,4")])

;; One's complement, 16 bit integers
(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(not:HI (match_operand:HI 1 "register_operand" "0")))]
  ""
  "not %0")


;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer arithmetic
;; ::
;; ::::::::::::::::::::

;; Addition
(define_insn_and_split "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_operand:SI 1 "register_operand" "%0")
		 (match_operand:SI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "#"
  "reload_completed"
  [(pc)]
  "{ xstormy16_expand_arith (SImode, PLUS, operands[0], operands[1],
			    operands[2], operands[3]); DONE; } "
  [(set_attr "length" "4")])

;; Subtraction
(define_insn_and_split "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "0")
		 (match_operand:SI 2 "nonmemory_operand" "ri")))
   (clobber (match_scratch:BI 3 "=y"))]
  ""
  "#"
  "reload_completed"
  [(pc)]
  "{ xstormy16_expand_arith (SImode, MINUS, operands[0], operands[1],
			    operands[2], operands[3]); DONE; } "
  [(set_attr "length" "4")])

(define_expand "negsi2"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (neg:SI (match_operand:SI 1 "register_operand" "")))
	      (clobber (match_scratch:BI 2 ""))])]
  ""
  "{ operands[2] = gen_reg_rtx (HImode);
     operands[3] = gen_reg_rtx (BImode); }")

(define_insn_and_split "*negsi2_internal"
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(neg:SI (match_operand:SI 1 "register_operand" "r")))
   (clobber (match_scratch:BI 2 "=y"))]
  ""
  "#"
  "reload_completed"
  [(pc)]
  "{ xstormy16_expand_arith (SImode, NEG, operands[0], operands[0],
			    operands[1], operands[2]); DONE; }")

;; ::::::::::::::::::::
;; ::
;; :: 32 bit Integer Shifts and Rotates
;; ::
;; ::::::::::::::::::::

;; Arithmetic Shift Left
(define_expand "ashlsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (ashift:SI (match_operand:SI 1 "register_operand" "")
			      (match_operand:SI 2 "const_int_operand" "")))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  " if (! const_int_operand (operands[2], SImode)) FAIL;
  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")

;; Arithmetic Shift Right
(define_expand "ashrsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
			        (match_operand:SI 2 "const_int_operand" "")))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  " if (! const_int_operand (operands[2], SImode)) FAIL;
  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")

;; Logical Shift Right
(define_expand "lshrsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
		   (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
			        (match_operand:SI 2 "const_int_operand" "")))
	      (clobber (match_dup 3))
	      (clobber (match_dup 4))])]
  ""
  " if (! const_int_operand (operands[2], SImode)) FAIL;
  operands[3] = gen_reg_rtx (BImode); operands[4] = gen_reg_rtx (HImode); ")

(define_insn "*shiftsi"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(match_operator:SI 5 "shift_operator"
	 [(match_operand:SI 1 "register_operand" "0,0")
	  (match_operand:SI 2 "const_int_operand" "U,n")]))
   (clobber (match_operand:BI 3 "register_operand" "=y,y"))
   (clobber (match_operand:HI 4 "" "=X,r"))]
  ""
  "* return xstormy16_output_shift (SImode, GET_CODE (operands[5]), 
				   operands[0], operands[2], operands[4]);"
  [(set_attr "length" "6,10")
   (set_attr "psw_operand" "clobber,clobber")])


;; ::::::::::::::::::::
;; ::
;; :: Comparisons
;; ::
;; ::::::::::::::::::::

;; Note, we store the operands in the comparison insns, and use them later
;; when generating the branch or scc operation.

;; First the routines called by the machine independent part of the compiler
(define_expand "cmphi"
  [(set (cc0)
        (compare (match_operand:HI 0 "register_operand" "")
  		 (match_operand:HI 1 "nonmemory_operand" "")))]
  ""
  "
{
  xstormy16_compare_op0 = operands[0];
  xstormy16_compare_op1 = operands[1];
  DONE;
}")

; There are no real SImode comparisons, but some can be emulated
; by performing a SImode subtract and looking at the condition flags.
(define_expand "cmpsi"
  [(set (cc0)
        (compare (match_operand:SI 0 "register_operand" "")
  		 (match_operand:SI 1 "nonmemory_operand" "")))]
  ""
  "
{
  xstormy16_compare_op0 = operands[0];
  xstormy16_compare_op1 = operands[1];
  DONE;
}")


;; ::::::::::::::::::::
;; ::
;; :: Branches
;; ::
;; ::::::::::::::::::::

(define_expand "beq"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (EQ, operands[0]); DONE; }")

(define_expand "bne"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (NE, operands[0]); DONE; }")

(define_expand "bge"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GE, operands[0]); DONE; }")

(define_expand "bgt"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GT, operands[0]); DONE; }")

(define_expand "ble"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LE, operands[0]); DONE; }")

(define_expand "blt"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LT, operands[0]); DONE; }")

(define_expand "bgeu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GEU, operands[0]); DONE; }")

(define_expand "bgtu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (GTU, operands[0]); DONE; }")

(define_expand "bleu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LEU, operands[0]); DONE; }")

(define_expand "bltu"
  [(use (match_operand 0 "" ""))]
  ""
  "{ xstormy16_emit_cbranch (LTU, operands[0]); DONE; }")


(define_insn "cbranchhi"
  [(set (pc) 
	(if_then_else (match_operator:HI 1 "comparison_operator"
				      [(match_operand:HI 2 "nonmemory_operand" 
					"r,e,L")
				       (match_operand:HI 3 "nonmemory_operand"
						      "r,L,e")])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
   (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
  ""
  "*
{
  return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 0, insn);
}"
  [(set_attr "branch_class" "bcc12")
   (set_attr "psw_operand" "0,0,1")])

(define_insn "cbranchhi_neg"
  [(set (pc) 
	(if_then_else (match_operator:HI 1 "comparison_operator"
				      [(match_operand:HI 2 "nonmemory_operand" 
							 "r,e,L")
				       (match_operand:HI 3 "nonmemory_operand"
							 "r,L,e")])
		      (pc)
		      (label_ref (match_operand 0 "" ""))))
   (clobber (match_operand:BI 4 "" "=&y,&y,&y"))]
  ""
  "*
{
  return xstormy16_output_cbranch_hi (operands[1], \"%l0\", 1, insn);
}"
  [(set_attr "branch_class" "bcc12")
   (set_attr "psw_operand" "0,0,1")])

(define_insn "*eqbranchsi"
  [(set (pc)
	(if_then_else (match_operator:SI 1 "equality_operator"
				      [(match_operand:SI 2 "register_operand" 
							 "r")
				       (const_int 0)])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
;; Although I would greatly like the 'match_dup' in the following line
;; to actually be a register constraint, there is (at the time of writing) no
;; way for reload to insert an output reload on the edges out of a branch.
;; If reload is fixed to use insert_insn_on_edge, this can be changed.
   (clobber (match_dup 2))]
  ""
  "*
{
  return xstormy16_output_cbranch_si (operands[1], \"%l0\", 0, insn);
}"
  [(set_attr "branch_class" "bcc8p2")
   (set_attr "psw_operand" "clobber")])

(define_insn_and_split "*ineqbranchsi"
  [(set (pc)
	(if_then_else (match_operator:SI 1 "xstormy16_ineqsi_operator"
				      [(match_operand:SI 2 "register_operand" 
							 "r")
				       (match_operand:SI 3 "nonmemory_operand" 
							 "ri")])
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
;; Although I would greatly like the 'match_dup' in the following line
;; to actually be a register constraint, there is (at the time of writing) no
;; way for reload to insert an output reload on the edges out of a branch.
;; If reload is fixed to use insert_insn_on_edge, this can be changed,
;; preferably to a 'minus' operand that explains the actual operation, like:
; (set (match_operand 5 "register_operand" "=2")
;      (minus:SI (match_operand 6 "register_operand" "2")
;		 (match_operand 7 "register_operand" "3")))
   (clobber (match_dup 2))