h8300.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxu.b\\t%X2,%T0\";
  else
    return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
}"
  [(set_attr "length" "4")])

(define_insn "divmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (div:HI
	    (match_operand:HI 1 "register_operand" "0")
	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
   (set (match_operand:QI 3 "register_operand" "=r")
	(truncate:QI
	  (mod:HI
	    (match_dup 1)
	    (sign_extend:HI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxs.b\\t%X2,%T0\";
  else
    return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
}"
  [(set_attr "length" "6")])

(define_insn "udivmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (udiv:SI
	    (match_operand:SI 1 "register_operand" "0")
	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
   (set (match_operand:HI 3 "register_operand" "=r")
	(truncate:HI
	  (umod:SI
	    (match_dup 1)
	    (zero_extend:SI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxu.w\\t%T2,%S0\";
  else
    return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
}"
  [(set_attr "length" "4")])

(define_insn "divmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (div:SI
	    (match_operand:SI 1 "register_operand" "0")
	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
   (set (match_operand:HI 3 "register_operand" "=r")
	(truncate:HI
	  (mod:SI
	    (match_dup 1)
	    (sign_extend:SI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxs.w\\t%T2,%S0\";
  else
    return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
}"
  [(set_attr "length" "6")])

;; ----------------------------------------------------------------------
;; AND INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "*andqi3_2"
  [(set (match_operand:QI 0 "bit_operand" "=rQ,r")
	(and:QI (match_operand:QI 1 "bit_operand" "%0,WU")
		(match_operand:QI 2 "h8300_src_operand" "rQi,IP1>X")))]
  "TARGET_H8300SX"
  "@
   and	%X2,%X0
   bfld	%2,%1,%R0"
  [(set_attr "length" "*,8")
   (set_attr "length_table" "logicb,*")
   (set_attr "cc" "set_znv,none_0hit")])

(define_insn "andqi3_1"
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "h8300_src_operand" "rn,n")))]
  "register_operand (operands[0], QImode)
   || single_zero_operand (operands[2], QImode)"
  "@
   and	%X2,%X0
   bclr	%W2,%R0"
  [(set_attr "length" "2,8")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "andqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(and:QI (match_operand:QI 1 "register_operand" "")
		(match_operand:QI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_expand "andhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(and:HI (match_operand:HI 1 "register_operand" "")
		(match_operand:HI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_insn "*andorqi3"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(ior:QI (and:QI (match_operand:QI 2 "register_operand" "r")
			(match_operand:QI 3 "single_one_operand" "n"))
		(match_operand:QI 1 "register_operand" "0")))]
  ""
  "bld\\t%V3,%X2\;bor\\t%V3,%X0\;bst\\t%V3,%X0"
  [(set_attr "length" "6")])

(define_insn "*andorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
			(match_operand:HI 3 "single_one_operand" "n"))
		(match_operand:HI 1 "register_operand" "0")))]
  ""
  "*
{
  operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
  if (INTVAL (operands[3]) > 128)
    {
      operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
      return \"bld\\t%V3,%t2\;bor\\t%V3,%t0\;bst\\t%V3,%t0\";
    }
  return \"bld\\t%V3,%s2\;bor\\t%V3,%s0\;bst\\t%V3,%s0\";
}"
  [(set_attr "length" "6")])

(define_insn "*andorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (and:SI (match_operand:SI 2 "register_operand" "r")
			(match_operand:SI 3 "single_one_operand" "n"))
		(match_operand:SI 1 "register_operand" "0")))]
  "(INTVAL (operands[3]) & 0xffff) != 0"
  "*
{
  operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
  if (INTVAL (operands[3]) > 128)
    {
      operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
      return \"bld\\t%V3,%x2\;bor\\t%V3,%x0\;bst\\t%V3,%x0\";
    }
  return \"bld\\t%V3,%w2\;bor\\t%V3,%w0\;bst\\t%V3,%w0\";
}"
  [(set_attr "length" "6")])

(define_insn "*andorsi3_shift_8"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r")
				   (const_int 8))
			(const_int 65280))
		(match_operand:SI 1 "register_operand" "0")))]
  ""
  "or.b\\t%w2,%x0"
  [(set_attr "length" "2")])

(define_expand "andsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(and:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "h8300_src_operand" "")))]
  ""
  "")

;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "iorqi3_1"
  [(set (match_operand:QI 0 "bit_operand" "=rQ,U")
	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
  "TARGET_H8300SX || register_operand (operands[0], QImode)
   || single_one_operand (operands[2], QImode)"
  "@
   or\\t%X2,%X0
   bset\\t%V2,%R0"
  [(set_attr "length" "*,8")
   (set_attr "length_table" "logicb,*")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "iorqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(ior:QI (match_operand:QI 1 "register_operand" "")
		(match_operand:QI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_expand "iorhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(ior:HI (match_operand:HI 1 "register_operand" "")
		(match_operand:HI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_expand "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ior:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "h8300_src_operand" "")))]
  ""
  "")

;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "xorqi3_1"
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "h8300_src_operand" "rQi,n")))]
  "TARGET_H8300SX || register_operand (operands[0], QImode)
   || single_one_operand (operands[2], QImode)"
  "@
   xor\\t%X2,%X0
   bnot\\t%V2,%R0"
  [(set_attr "length" "*,8")
   (set_attr "length_table" "logicb,*")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "xorqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(xor:QI (match_operand:QI 1 "register_operand" "")
		(match_operand:QI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_expand "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(xor:HI (match_operand:HI 1 "register_operand" "")
		(match_operand:HI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_expand "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(xor:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "h8300_src_operand" "")))]
  ""
  "")

;; ----------------------------------------------------------------------
;; {AND,IOR,XOR}{HI3,SI3} PATTERNS
;; ----------------------------------------------------------------------

;; We need a separate pattern here because machines other than the
;; original H8300 don't have to split the 16-bit operand into a pair
;; of high/low instructions, so we can accept literal addresses, that
;; have to be loaded into a register on H8300.
(define_insn "*logicalhi3_sn"
  [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
	(match_operator:HI 3 "bit_operator"
	  [(match_operand:HI 1 "h8300_dst_operand" "%0")
	   (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
  "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
  "* return output_logical_op (HImode, operands);"
  [(set (attr "length")
	(symbol_ref "compute_logical_op_length (HImode, operands)"))
   (set (attr "cc")
	(symbol_ref "compute_logical_op_cc (HImode, operands)"))])

(define_insn "*logicalsi3_sn"
  [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
	(match_operator:SI 3 "bit_operator"
	  [(match_operand:SI 1 "h8300_dst_operand" "%0")
	   (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
  "(TARGET_H8300S || TARGET_H8300H) && h8300_operands_match_p (operands)"
  "* return output_logical_op (SImode, operands);"
  [(set (attr "length")
	(symbol_ref "compute_logical_op_length (SImode, operands)"))
   (set (attr "cc")
	(symbol_ref "compute_logical_op_cc (SImode, operands)"))])

(define_insn "*logicalhi3"
  [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
	(match_operator:HI 3 "bit_operator"
	  [(match_operand:HI 1 "h8300_dst_operand" "%0")
	   (match_operand:HI 2 "h8300_src_operand" "rQi")]))]
  "h8300_operands_match_p (operands)"
  "* return output_logical_op (HImode, operands);"
  [(set (attr "length")
	(symbol_ref "compute_logical_op_length (HImode, operands)"))
   (set (attr "cc")
	(symbol_ref "compute_logical_op_cc (HImode, operands)"))])

(define_insn "*logicalsi3"
  [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
	(match_operator:SI 3 "bit_operator"
	  [(match_operand:SI 1 "h8300_dst_operand" "%0")
	   (match_operand:SI 2 "h8300_src_operand" "rQi")]))]
  "h8300_operands_match_p (operands)"
  "* return output_logical_op (SImode, operands);"
  [(set (attr "length")
	(symbol_ref "compute_logical_op_length (SImode, operands)"))
   (set (attr "cc")
	(symbol_ref "compute_logical_op_cc (SImode, operands)"))])

;; ----------------------------------------------------------------------
;; NEGATION INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_expand "negqi2"
  [(set (match_operand:QI 0 "register_operand" "")
	(neg:QI (match_operand:QI 1 "register_operand" "")))]
  ""
  "")

(define_insn "*negqi2"
  [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
	(neg:QI (match_operand:QI 1 "h8300_dst_operand" "0")))]
  ""
  "neg	%X0"
  [(set_attr "length_table" "unary")
   (set_attr "cc" "set_zn")])

(define_expand "neghi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(neg:HI (match_operand:HI 1 "register_operand" "")))]
  ""
  "
{
  if (TARGET_H8300)
    {
      emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
      DONE;
    }
}")

(define_expand "neghi2_h8300"
  [(set (match_dup 2)
	(not:HI (match_operand:HI 1 "register_operand" "")))
   (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
   (set (match_operand:HI 0 "register_operand" "")
	(match_dup 2))]
  ""
  "operands[2] = gen_reg_rtx (HImode);")

(define_insn "*neghi2_h8300hs"
  [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ")
	(neg:HI (match_operand:HI 1 "h8300_dst_operand" "0")))]
  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
  "neg.w	%T0"
  [(set_attr "length_table" "unary")
   (set_attr "cc" "set_zn")])

(define_expand "negsi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(neg:SI (match_operand:SI 1 "register_operand" "")))]
  ""
  "
{
  if (TARGET_H8300)
    {
      emit_insn (gen_negsi2_h8300 (operands[0], operands[1]));
      DONE;
    }
}")

(define_expand "negsi2_h8300"
  [(set (match_dup 2)
	(not:SI (match_operand:SI 1 "register_operand" "")))
   (set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
   (set (match_operand:SI 0 "register_operand" "")
	(match_dup 2))]
  ""
  "operands[2] = gen_reg_rtx (SImode);")

(define_insn "*negsi2_h8300hs"
  [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ")
	(neg:SI (match_operand:SI 1 "h8300_dst_operand" "0")))]
  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
  "neg.l	%S0"
  [(set_attr "length_table" "unary")
   (set_attr "cc" "set_zn")])

(define_expand "negsf2"
  [(set (match_operand:SF 0 "register_operand" "")
	(neg:SF (match_operand:SF 1 "register_operand" "")))]
  ""
  "")

(define_insn "*negsf2_h8300"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
  "TARGET_H8300"
  "xor.b\\t#128,%z0"
  [(set_attr "length" "2")])

(define_insn "*negsf2_h8300hs"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(neg:SF (match_operand:SF 1 "register_operand" "0")))]
  "TARGET_H8300H || TARGET_H8300S"
  "xor.w\\t#32768,%e0"
  [(set_attr "length" "4")])

;; ----------------------------------------------------------------------
;; ABSOLUTE VALUE INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_expand "abssf2"
  [(set (match_operand:SF 0 "register_operand" "")
	(abs:SF (m