h8300.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

		   UNSPEC_INCDEC))]
  "TARGET_H8300H || TARGET_H8300S"
  "@
   inc.w	%2,%T0
   dec.w	%G2,%T0"
  [(set_attr "length" "2,2")
   (set_attr "cc" "set_zn,set_zn")])

(define_insn "*addhi3_h8sx"
  [(set (match_operand:HI 0 "h8300_dst_operand" "=rU,rU,r,rQ")
	(plus:HI (match_operand:HI 1 "h8300_dst_operand" "%0,0,0,0")
		 (match_operand:HI 2 "h8300_src_operand" "P3>X,P3<X,J,rQi")))]
  "TARGET_H8300SX && h8300_operands_match_p (operands)"
  "@
   add.w	%T2,%T0
   sub.w	%G2,%T0
   add.b	%t2,%t0
   add.w	%T2,%T0"
  [(set_attr "length_table" "short_immediate,short_immediate,*,addw")
   (set_attr "length" "*,*,2,*")
   (set_attr "cc" "set_zn")])

(define_split
  [(set (match_operand:HI 0 "register_operand" "")
	(plus:HI (match_dup 0)
		 (match_operand:HI 1 "two_insn_adds_subs_operand" "")))]
  ""
  [(const_int 0)]
  "split_adds_subs (HImode, operands); DONE;")

(define_expand "addsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "register_operand" "")
		 (match_operand:SI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_insn "*addsi_h8300"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(plus:SI (match_operand:SI 1 "register_operand" "%0,0")
		 (match_operand:SI 2 "h8300_src_operand" "n,r")))]
  "TARGET_H8300"
  "* return output_plussi (operands);"
  [(set (attr "length")
	(symbol_ref "compute_plussi_length (operands)"))
   (set (attr "cc")
	(symbol_ref "compute_plussi_cc (operands)"))])

(define_insn "*addsi_h8300hs"
  [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
	(plus:SI (match_operand:SI 1 "h8300_dst_operand" "%0,0")
		 (match_operand:SI 2 "h8300_src_operand" "i,rQ")))]
  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
  "* return output_plussi (operands);"
  [(set (attr "length")
	(symbol_ref "compute_plussi_length (operands)"))
   (set (attr "cc")
	(symbol_ref "compute_plussi_cc (operands)"))])

(define_insn "*addsi3_incdec"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(unspec:SI [(match_operand:SI 1 "register_operand" "0,0")
		    (match_operand:SI 2 "incdec_operand" "M,O")]
		   UNSPEC_INCDEC))]
  "TARGET_H8300H || TARGET_H8300S"
  "@
   inc.l	%2,%S0
   dec.l	%G2,%S0"
  [(set_attr "length" "2,2")
   (set_attr "cc" "set_zn,set_zn")])

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_dup 0)
		 (match_operand:SI 1 "two_insn_adds_subs_operand" "")))]
  "TARGET_H8300H || TARGET_H8300S"
  [(const_int 0)]
  "split_adds_subs (SImode, operands); DONE;")

;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_expand "subqi3"
  [(set (match_operand:QI 0 "register_operand" "")
	(minus:QI (match_operand:QI 1 "register_operand" "")
		  (match_operand:QI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_insn "*subqi3"
  [(set (match_operand:QI 0 "h8300_dst_operand" "=rQ")
	(minus:QI (match_operand:QI 1 "h8300_dst_operand" "0")
		  (match_operand:QI 2 "h8300_dst_operand" "rQ")))]
  "h8300_operands_match_p (operands)"
  "sub.b	%X2,%X0"
  [(set_attr "length_table" "addb")
   (set_attr "cc" "set_zn")])

(define_expand "subhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(minus:HI (match_operand:HI 1 "register_operand" "")
		  (match_operand:HI 2 "h8300_src_operand" "")))]
  ""
  "")

(define_insn "*subhi3_h8300"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(minus:HI (match_operand:HI 1 "register_operand" "0,0")
		  (match_operand:HI 2 "h8300_src_operand" "r,n")))]
  "TARGET_H8300"
  "@
   sub.w	%T2,%T0
   add.b	%E2,%s0\;addx	%F2,%t0"
  [(set_attr "length" "2,4")
   (set_attr "cc" "set_zn,clobber")])

(define_insn "*subhi3_h8300hs"
  [(set (match_operand:HI 0 "h8300_dst_operand" "=rQ,rQ")
	(minus:HI (match_operand:HI 1 "h8300_dst_operand" "0,0")
		  (match_operand:HI 2 "h8300_src_operand" "rQ,i")))]
  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
  "@
   sub.w	%T2,%T0
   sub.w	%T2,%T0"
  [(set_attr "length_table" "addw")
   (set_attr "cc" "set_zn")])

(define_expand "subsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(minus:SI (match_operand:SI 1 "register_operand" "")
		  (match_operand:SI 2 "h8300_src_operand" "")))]
  ""
{
  if (TARGET_H8300)
    operands[2] = force_reg (SImode, operands[2]);
})

(define_insn "*subsi3_h8300"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "0")
		  (match_operand:SI 2 "register_operand" "r")))]
  "TARGET_H8300"
  "sub.w	%f2,%f0\;subx	%y2,%y0\;subx	%z2,%z0"
  [(set_attr "length" "6")])

(define_insn "*subsi3_h8300hs"
  [(set (match_operand:SI 0 "h8300_dst_operand" "=rQ,rQ")
	(minus:SI (match_operand:SI 1 "h8300_dst_operand" "0,0")
		  (match_operand:SI 2 "h8300_src_operand" "rQ,i")))]
  "(TARGET_H8300H || TARGET_H8300S) && h8300_operands_match_p (operands)"
  "@
   sub.l	%S2,%S0
   sub.l	%S2,%S0"
  [(set_attr "length_table" "addl")
   (set_attr "cc" "set_zn")])

;; ----------------------------------------------------------------------
;; MULTIPLY INSTRUCTIONS
;; ----------------------------------------------------------------------

;; Note that the H8/300 can only handle umulqihi3.

(define_expand "mulqihi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" ""))
		 ;; intentionally-mismatched modes
		 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
  "TARGET_H8300H || TARGET_H8300S"
  "
{
  if (GET_MODE (operands[2]) != VOIDmode)
    operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]);
}")

(define_insn "*mulqihi3_const"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
		 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
  "TARGET_H8300SX"
  "mulxs.b	%X2,%T0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_zn")])

(define_insn "*mulqihi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
		 (sign_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
  "TARGET_H8300H || TARGET_H8300S"
  "mulxs.b	%X2,%T0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_zn")])

(define_expand "mulhisi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
		 ;; intentionally-mismatched modes
		 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
  "TARGET_H8300H || TARGET_H8300S"
  "
{
  if (GET_MODE (operands[2]) != VOIDmode)
    operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]);
}")

(define_insn "*mulhisi3_const"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
		 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
  "TARGET_H8300SX"
  "mulxs.w	%T2,%S0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_zn")])

(define_insn "*mulhisi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
		 (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
  "TARGET_H8300H || TARGET_H8300S"
  "mulxs.w	%T2,%S0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_zn")])

(define_expand "umulqihi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" ""))
		 ;; intentionally-mismatched modes
		 (match_operand:QI 2 "reg_or_nibble_operand" "")))]
  "TARGET_H8300H || TARGET_H8300S"
  "
{
  if (GET_MODE (operands[2]) != VOIDmode)
    operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]);
}")

(define_insn "*umulqihi3_const"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
		 (match_operand:QI 2 "nibble_operand" "IP4>X")))]
  "TARGET_H8300SX"
  "mulxu.b	%X2,%T0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_zn")])

(define_insn "*umulqihi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
		 (zero_extend:HI (match_operand:QI 2 "register_operand" "r"))))]
  ""
  "mulxu.b	%X2,%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "none_0hit")])

(define_expand "umulhisi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
		 ;; intentionally-mismatched modes
		 (match_operand:HI 2 "reg_or_nibble_operand" "")))]
  "TARGET_H8300H || TARGET_H8300S"
  "
{
  if (GET_MODE (operands[2]) != VOIDmode)
    operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]);
}")

(define_insn "*umulhisi3_const"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
		 (match_operand:SI 2 "nibble_operand" "IP4>X")))]
  "TARGET_H8300SX"
  "mulxu.w	%T2,%S0"
  [(set_attr "length" "4")
   (set_attr "cc" "set_zn")])

(define_insn "*umulhisi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%0"))
		 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
  "TARGET_H8300H || TARGET_H8300S"
  "mulxu.w	%T2,%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "none_0hit")])

;; We could have used mulu.[wl] here, but mulu.[lw] is only available
;; on a H8SX with a multiplier, whereas muls.w seems to be available
;; on all H8SX variants.
(define_insn "mulhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
        (mult:HI (match_operand:HI 1 "register_operand" "%0")
		 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
  "TARGET_H8300SX"
  "muls.w\\t%T2,%T0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
        (mult:SI (match_operand:SI 1 "register_operand" "%0")
		 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
  "TARGET_H8300SX"
  "muls.l\\t%S2,%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn "smulsi3_highpart"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(truncate:SI
	 (lshiftrt:DI
	  (mult:DI
	   (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
	   (sign_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
	  (const_int 32))))]
  "TARGET_H8300SXMUL"
  "muls/u.l\\t%S2,%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_insn "umulsi3_highpart"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(truncate:SI
	 (ashiftrt:DI
	  (mult:DI
	   (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
	   (zero_extend:DI (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))
	  (const_int 32))))]
  "TARGET_H8300SX"
  "mulu/u.l\\t%S2,%S0"
  [(set_attr "length" "2")
   (set_attr "cc" "none_0hit")])

;; This is a "bridge" instruction.  Combine can't cram enough insns
;; together to crate a MAC instruction directly, but it can create
;; this instruction, which then allows combine to create the real
;; MAC insn.
;;
;; Unfortunately, if combine doesn't create a MAC instruction, this
;; insn must generate reasonably correct code.  Egad.
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a")
	(mult:SI
	  (sign_extend:SI
	    (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
	  (sign_extend:SI
	    (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
  "TARGET_MAC"
  "clrmac\;mac	@%2+,@%1+"
  [(set_attr "length" "6")
   (set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a")
	(plus:SI (mult:SI
	  (sign_extend:SI (mem:HI
	    (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
	  (sign_extend:SI (mem:HI
	    (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
	      (match_operand:SI 3 "register_operand" "0")))]
  "TARGET_MAC"
  "mac	@%2+,@%1+"
  [(set_attr "length" "4")
   (set_attr "cc" "none_0hit")])

;; ----------------------------------------------------------------------
;; DIVIDE/MOD INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "udivhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(udiv:HI
	 (match_operand:HI 1 "register_operand" "0")
	 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
  "TARGET_H8300SX"
  "divu.w\\t%T2,%T0"
  [(set_attr "length" "2")])
  
(define_insn "divhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(div:HI
	 (match_operand:HI 1 "register_operand" "0")
	 (match_operand:HI 2 "reg_or_nibble_operand" "r IP4>X")))]
  "TARGET_H8300SX"
  "divs.w\\t%T2,%T0"
  [(set_attr "length" "2")])
  
(define_insn "udivsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(udiv:SI
	 (match_operand:SI 1 "register_operand" "0")
	 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
  "TARGET_H8300SX"
  "divu.l\\t%S2,%S0"
  [(set_attr "length" "2")])
  
(define_insn "divsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(div:SI
	 (match_operand:SI 1 "register_operand" "0")
	 (match_operand:SI 2 "reg_or_nibble_operand" "r IP4>X")))]
  "TARGET_H8300SX"
  "divs.l\\t%S2,%S0"
  [(set_attr "length" "2")])
  
(define_insn "udivmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (udiv:HI
	    (match_operand:HI 1 "register_operand" "0")
	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
   (set (match_operand:QI 3 "register_operand" "=r")
	(truncate:QI
	  (umod:HI
	    (match_dup 1)
	    (zero_extend:HI (match_dup 2)))))]
  ""
  "*