m68hc11.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;;--------------------------------------------------------------------
;;- Add instructions.
;;--------------------------------------------------------------------
;; 64-bit: Use a library call because what GCC generates is huge.
;;
(define_expand "adddi3"
  [(set (match_operand:DI 0 "nonimmediate_operand" "")
	(plus:DI (match_operand:DI 1 "general_operand" "")
		 (match_operand:DI 2 "general_operand" "")))]
  ""
  "m68hc11_emit_libcall (\"___adddi3\", PLUS, DImode, DImode, 3, operands);
   DONE;")

;;
;; - 32-bit Add.
;;
(define_expand "addsi3"
  [(parallel [(set (match_operand:SI 0 "register_operand" "")
	             (plus:SI (match_operand:SI 1 "general_operand" "")
		              (match_operand:SI 2 "general_operand" "")))
              (clobber (match_scratch:HI 3 ""))])]
  ""
  "")

(define_insn "*addsi3_zero_extendhi"
  [(set (match_operand:SI 0 "register_operand" "=D,D,D,D")
	(plus:SI (zero_extend:SI 
		 (match_operand:HI 1 "general_operand" "dxi,!u,mdxi,!u"))
		 (match_operand:SI 2 "general_operand" "mi,mi,D?u,!Du")))
   (clobber (match_scratch:HI 3 "=X,X,X,X"))]
  ""
  "*
{
  rtx ops[3];

  if (X_REG_P (operands[2]))
    {
      ops[0] = operands[1];
    }
  else
    {
      if (X_REG_P (operands[1]))
        {
          output_asm_insn (\"xgdx\", ops);
        }
      else if (!D_REG_P (operands[1]))
        {
          ops[0] = gen_rtx_REG (HImode, HARD_D_REGNUM);
          ops[1] = operands[1];
          m68hc11_gen_movhi (insn, ops);
        }
      ops[0] = m68hc11_gen_lowpart (HImode, operands[2]);
      ops[1] = m68hc11_gen_highpart (HImode, operands[2]);
    }
  ops[2] = gen_label_rtx ();

  /* ldx preserves the carry, propagate it by incrementing X directly.  */
  output_asm_insn (\"addd\\t%0\", ops);
  if (!X_REG_P (operands[2]))
    output_asm_insn (\"ldx\\t%1\", ops);

  output_asm_insn (\"bcc\\t%l2\", ops);
  output_asm_insn (\"inx\", ops);

  CC_STATUS_INIT;
  (*targetm.asm_out.internal_label) (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[2]));
  return \"\";  
}")


(define_split /* "*addsi3_zero_extendqi" */
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (zero_extend:SI 
		   (match_operand:QI 1 "general_operand" ""))
		 (match_operand:SI 2 "memory_operand" "")))
   (clobber (match_scratch:HI 3 "=X,X"))]
  "reload_completed"
  [(set (reg:HI D_REGNUM) (zero_extend:HI (match_dup 1)))
   (parallel [(set (match_dup 0) 
		   (plus:SI (zero_extend:SI (reg:HI D_REGNUM)) (match_dup 2)))
	      (clobber (match_dup 3))])]
  "")

(define_insn "*addsi3_zero_extendqi"
  [(set (match_operand:SI 0 "register_operand" "=D,D")
	(plus:SI (zero_extend:SI 
		   (match_operand:QI 1 "general_operand" "dAmi,!dAmiu"))
		 (match_operand:SI 2 "general_operand" "miD,!muiD")))
   (clobber (match_scratch:HI 3 "=X,X"))]
  ""
  "*
{
  rtx ops[4];

  if (GET_CODE (operands[2]) == MEM)
    return \"#\";

  if (X_REG_P (operands[2]))
    {
      if (H_REG_P (operands[1]))
	{
	  ops[0] = gen_rtx_REG (HImode, SOFT_TMP_REGNUM);
	  ops[1] = gen_rtx_REG (HImode, REGNO (operands[1]));
	  m68hc11_gen_movhi (insn, ops);
	}
      else
	{
	  ops[0] = operands[1];
	}
      ops[1] = const0_rtx;
    }
  else
    {
      if (X_REG_P (operands[1]))
        {
          output_asm_insn (\"xgdx\", ops);
        }
      else if (!D_REG_P (operands[1]))
        {
          ops[0] = gen_rtx_REG (QImode, HARD_D_REGNUM);
          ops[1] = operands[1];
          m68hc11_gen_movqi (insn, ops);
        }

      ops[0] = m68hc11_gen_lowpart (HImode, operands[2]);
      ops[1] = ops[0];
      ops[2] = m68hc11_gen_highpart (HImode, operands[2]);
      output_asm_insn (\"clra\", ops);
    }

  /* ldx preserves the carry, propagate it by incrementing X directly.  */
  output_asm_insn (\"addb\\t%b0\", ops);
  output_asm_insn (\"adca\\t%h1\", ops);
  if (!X_REG_P (operands[2]))
    output_asm_insn (\"ldx\\t%2\", ops);

  /* If the above adca was adding some constant, we don't need to propagate
     the carry unless the constant was 0xff.  */
  if (X_REG_P (operands[2])
      || GET_CODE (ops[1]) != CONST_INT
      || ((INTVAL (ops[1]) & 0x0ff00) == 0x0ff00))
    {
      ops[3] = gen_label_rtx ();

      output_asm_insn (\"bcc\\t%l3\", ops);
      output_asm_insn (\"inx\", ops);

      (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
				 CODE_LABEL_NUMBER (ops[3]));
    }
  CC_STATUS_INIT;
  return \"\";  
}")

(define_insn "*addsi3"
  [(set (match_operand:SI 0 "non_push_operand" "=o,D,!u,?D,D")
	(plus:SI (match_operand:SI 1 "non_push_operand" "%0,0,0,0,0")
		 (match_operand:SI 2 "general_operand" "ML,i,ML,?D,?oiu")))
   (clobber (match_scratch:HI 3 "=d,X,d,X,X"))]
  ""
  "*
{
  rtx   ops[3];
  const char* add_insn;
  const char* inc_insn;
  const char* incb_mem;
  const char* inch_mem;
  HOST_WIDE_INT val;

  if (which_alternative > 2)
    {
      return \"#\";
    }

  val = INTVAL (operands[2]);
  if ((val & 0x0ffffL) == 0)
    {
      if (!H_REG_P (operands[0]))
	{
	  ops[0] = m68hc11_gen_highpart (HImode, operands[0]);
	  ops[1] = m68hc11_gen_highpart (HImode, operands[2]);
	  output_asm_insn (\"ldd\\t%0\", ops);
	  output_asm_insn (\"addd\\t%1\", ops);
	  output_asm_insn (\"std\\t%0\", ops);
	  return \"\";
	}
      else if (val == 1)
	{
	  return \"inx\";
	}
      else
	{
	  return \"#\";
	}
    }
  if ((val & 0xffff0000L) != 0 && (val & 0xffff0000L) != 0xffff0000L)
    {
      return \"#\";
    }

  if (val >= 0)
    {
      ops[1]   = operands[2];
      add_insn = \"addd\\t%1\";
      inc_insn = \"inx\\t\";
      incb_mem  = \"inc\\t%b1\";
      inch_mem  = \"inc\\t%h1\";
    }
  else
    {
      ops[1] = GEN_INT (- val);
      add_insn = \"subd\\t%1\";
      inc_insn = \"dex\";
      incb_mem  = \"dec\\t%b1\";
      inch_mem  = \"dec\\t%h1\";
    }
      
  ops[2] = gen_label_rtx ();
  if (!H_REG_P (operands[0]))
    {
      ops[0] = m68hc11_gen_lowpart (HImode, operands[0]);
      output_asm_insn (\"ldd\\t%0\", ops);
    }
  output_asm_insn (add_insn, ops);
  if (!H_REG_P (operands[0]))
    {
      output_asm_insn (\"std\\t%0\", ops);
    }
  output_asm_insn (\"bcc\\t%l2\", ops);
  if (H_REG_P (operands[0]))
    {
      output_asm_insn (inc_insn, ops);
    }
  else
    {
      ops[0] = m68hc11_gen_highpart (HImode, operands[0]);
      ops[1] = ops[0];
      if (INTVAL (operands[2]) < 0)
	{
	  output_asm_insn (\"ldd\\t%1\", ops);
	  output_asm_insn (\"addd\\t#-1\", ops);
	  output_asm_insn (\"std\\t%1\", ops);
	}
      else
	{
          output_asm_insn (incb_mem, ops);
          output_asm_insn (\"bne\\t%l2\", ops);
          output_asm_insn (inch_mem, ops);
	}
    }
  (*targetm.asm_out.internal_label) (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[2]));

  CC_STATUS_INIT;
  return \"\";
}")

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "register_operand" "")
		 (match_operand:SI 2 "const_int_operand" "")))
   (clobber (match_scratch:HI 3 ""))]
  "reload_completed && z_replacement_completed == 2
   && ((INTVAL (operands[2]) & 0x0FFFF) == 0)"
  [(set (match_dup 5) (match_dup 6))
   (set (reg:HI 0) (plus:HI (reg:HI 0) (match_dup 4)))
   (set (match_dup 6) (match_dup 5))]
  "operands[4] = m68hc11_gen_highpart (HImode, operands[2]);
   if (X_REG_P (operands[0]))
     {
       operands[5] = operands[6] = gen_rtx_REG (HImode, HARD_D_REGNUM);
     }
   else
     {
       operands[6] = m68hc11_gen_highpart (HImode, operands[1]);
       operands[5] = operands[3];
     }
   ")

(define_split
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "register_operand" "")
		 (match_operand:SI 2 "general_operand" "")))
   (clobber (match_scratch:HI 3 "=X"))]
  "reload_completed && z_replacement_completed == 2
   && (GET_CODE (operands[2]) != CONST_INT || 
        (!(INTVAL (operands[2]) >= -65536 && INTVAL (operands[2]) <= 65535)))"
  [(set (reg:HI D_REGNUM) (plus:HI (reg:HI D_REGNUM) (match_dup 3)))
   (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM))
              (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))])
   (set (reg:QI B_REGNUM) (plus:QI (plus:QI (reg:QI CC_REGNUM) (reg:QI B_REGNUM)) (match_dup 4)))
   (set (reg:QI A_REGNUM) (plus:QI (plus:QI (reg:QI CC_REGNUM) (reg:QI A_REGNUM)) (match_dup 5)))
   (parallel [(set (reg:HI D_REGNUM) (reg:HI X_REGNUM))
              (set (reg:HI X_REGNUM) (reg:HI D_REGNUM))])]
  "operands[3] = m68hc11_gen_lowpart (HImode, operands[2]);
   operands[4] = m68hc11_gen_highpart (HImode, operands[2]);
   operands[5] = m68hc11_gen_highpart (QImode, operands[4]);
   operands[4] = m68hc11_gen_lowpart (QImode, operands[4]);")

;;
;; Instruction generated to propagate the carry of a 16-bit add
;; to the upper 16-bit part (in register X).
;;
(define_insn "*addsi_carry"
  [(set (match_operand:HI 0 "register_operand" "=x")
           (plus:HI (plus:HI (match_operand:HI 1 "register_operand" "0")
		             (const_int 0)) 
		    (reg:HI CC_REGNUM)))]
  ""
  "*
{
  rtx ops[2];

  ops[0] = gen_label_rtx ();
  output_asm_insn (\"bcc\\t%l0\", ops);
  output_asm_insn (\"in%0\", operands);
  (*targetm.asm_out.internal_label) (asm_out_file, \"L\", CODE_LABEL_NUMBER (ops[0]));
  CC_STATUS_INIT;
  return \"\";
}")

;;
;; - 16-bit Add.
;;
(define_expand "addhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	   (plus:HI (match_operand:HI 1 "register_operand" "")
		    (match_operand:HI 2 "general_operand" "")))]
  ""
  "
{
  if (TARGET_M6811 && SP_REG_P (operands[0]))
    {
      emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
			 gen_rtx_SET (VOIDmode,
				  operand0,
				  gen_rtx_PLUS (HImode,
					   operand1, operand2)),
			gen_rtx_CLOBBER (VOIDmode,
				gen_rtx_SCRATCH (HImode)))));
      DONE;
    }
}")

(define_insn "*addhi3_68hc12"
  [(set (match_operand:HI 0 "register_operand" "=d*A,d,xy*A*w,xy*A*w,xy*A")
        (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,xy*Aw,0")
                 (match_operand:HI 2 "general_operand" "i,m*A*wu,id,id,!mu*A")))]
  "TARGET_M6812"
  "*
{
  int val;
  const char* insn_code;

  if (which_alternative >= 4)
    {
      if (A_REG_P (operands[2]))
        {
	  CC_STATUS_INIT;
	  output_asm_insn (\"xgd%2\", operands);
	  output_asm_insn (\"lea%0 d,%0\", operands);
	  return \"xgd%2\";
	}
      return \"#\";
    }

  if (D_REG_P (operands[0]))
    {
      if (X_REG_P (operands[2]))
	{
	  m68hc11_notice_keep_cc (operands[0]);
	  output_asm_insn (\"xgdx\", operands);
	  output_asm_insn (\"leax\\td,%2\", operands);
	  return \"xgdx\";
	}
      else if (Y_REG_P (operands[2]))
	{
	  m68hc11_notice_keep_cc (operands[0]);
	  output_asm_insn (\"xgdy\", operands);
	  output_asm_insn (\"leay\\td,%2\", operands);
	  return \"xgdy\";
	}
      else if (SP_REG_P (operands[2]))
	{
	  output_asm_insn (\"sts\\t%t0\", operands);
	  return \"addd\\t%t0\";
	}
      return \"addd\\t%2\";
    }

  if (GET_CODE (operands[2]) == CONST_INT)
    val = INTVAL (operands[2]);
  else
    val = 1000;

  if ((val != -1 && val != 1) || !rtx_equal_p (operands[0], operands[1]))
    {
      m68hc11_notice_keep_cc (operands[0]);
      switch (REGNO (operands[0]))
	{
	case HARD_X_REGNUM:
	  return \"leax\\t%i2,%1\";

	case HARD_Y_REGNUM:
	  return \"leay\\t%i2,%1\";

	case HARD_SP_REGNUM:
	  return \"leas\\t%i2,%1\";

	default:
	  fatal_insn (\"Invalid operands in the instruction\", insn);
	}
    }
  if (val > 0)
    {
      insn_code = X_REG_P (operands[0]) ? \"inx\"
		: Y_REG_P (operands[0]) ? \"iny\" : \"ins\";
    }
  else
    {
      val  = -val;
      insn_code = X_REG_P (operands[0]) ? \"dex\"
		: Y_REG_P (operands[0]) ? \"dey\" : \"des\";
    }

  /* For X and Y increment, the flags are not complete. Only the Z flag
     is updated. For SP increment, flags are not changed.  */
  if (SP_REG_P (operands[0]))
    {
      cc_status = cc_prev_status; 
      if (INTVAL (operands[2]) < 0)
	{
	  while (val > 2)