rs6000.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

			N_("Generate string instructions for block moves")},\
  {"no-string",		- MASK_STRING,					\
			N_("Do not generate string instructions for block moves")},\
  {"update",		- MASK_NO_UPDATE,				\
			N_("Generate load/store with update instructions")},\
  {"no-update",		MASK_NO_UPDATE,					\
			N_("Do not generate load/store with update instructions")},\
  {"fused-madd",	- MASK_NO_FUSED_MADD,				\
			N_("Generate fused multiply/add instructions")},\
  {"no-fused-madd",	MASK_NO_FUSED_MADD,				\
			N_("Do not generate fused multiply/add instructions")},\
  {"sched-prolog",      MASK_SCHED_PROLOG,                              \
			""},						\
  {"no-sched-prolog",   -MASK_SCHED_PROLOG,                             \
			N_("Do not schedule the start and end of the procedure")},\
  {"sched-epilog",      MASK_SCHED_PROLOG,                              \
			""},						\
  {"no-sched-epilog",   -MASK_SCHED_PROLOG,                             \
			""},						\
  {"aix-struct-return",	MASK_AIX_STRUCT_RET,				\
			N_("Return all structures in memory (AIX default)")},\
  {"svr4-struct-return", - MASK_AIX_STRUCT_RET,				\
			N_("Return small structures in registers (SVR4 default)")},\
  {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,			\
			""},						\
  {"no-svr4-struct-return", MASK_AIX_STRUCT_RET,			\
			""},						\
  {"mfcrf",		MASK_MFCRF,					\
			N_("Generate single field mfcr instruction")},	\
  {"no-mfcrf",		- MASK_MFCRF,					\
			N_("Do not generate single field mfcr instruction")},\
  SUBTARGET_SWITCHES							\
  {"",			TARGET_DEFAULT | MASK_SCHED_PROLOG,		\
			""}}

#define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)

/* This is meant to be redefined in the host dependent files */
#define SUBTARGET_SWITCHES

/* Processor type.  Order must match cpu attribute in MD file.  */
enum processor_type
 {
   PROCESSOR_RIOS1,
   PROCESSOR_RIOS2,
   PROCESSOR_RS64A,
   PROCESSOR_MPCCORE,
   PROCESSOR_PPC403,
   PROCESSOR_PPC405,
   PROCESSOR_PPC440,
   PROCESSOR_PPC601,
   PROCESSOR_PPC603,
   PROCESSOR_PPC604,
   PROCESSOR_PPC604e,
   PROCESSOR_PPC620,
   PROCESSOR_PPC630,
   PROCESSOR_PPC750,
   PROCESSOR_PPC7400,
   PROCESSOR_PPC7450,
   PROCESSOR_PPC8540,
   PROCESSOR_POWER4,
   PROCESSOR_POWER5
};

extern enum processor_type rs6000_cpu;

/* Recast the processor type to the cpu attribute.  */
#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)

/* Define generic processor types based upon current deployment.  */
#define PROCESSOR_COMMON    PROCESSOR_PPC601
#define PROCESSOR_POWER     PROCESSOR_RIOS1
#define PROCESSOR_POWERPC   PROCESSOR_PPC604
#define PROCESSOR_POWERPC64 PROCESSOR_RS64A

/* Define the default processor.  This is overridden by other tm.h files.  */
#define PROCESSOR_DEFAULT   PROCESSOR_RIOS1
#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A

/* Specify the dialect of assembler to use.  New mnemonics is dialect one
   and the old mnemonics are dialect zero.  */
#define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)

/* Types of costly dependences.  */
enum rs6000_dependence_cost
 {
   max_dep_latency = 1000,
   no_dep_costly,
   all_deps_costly,
   true_store_to_load_dep_costly,
   store_to_load_dep_costly
 };

/* Types of nop insertion schemes in sched target hook sched_finish.  */
enum rs6000_nop_insertion
  {
    sched_finish_regroup_exact = 1000,
    sched_finish_pad_groups,
    sched_finish_none
  };

/* Dispatch group termination caused by an insn.  */
enum group_termination
  {
    current_group,
    previous_group
  };

/* This is meant to be overridden in target specific files.  */
#define	SUBTARGET_OPTIONS

#define TARGET_OPTIONS							\
{									\
   {"cpu=",  &rs6000_select[1].string,					\
    N_("Use features of and schedule code for given CPU"), 0},		\
   {"tune=", &rs6000_select[2].string,					\
    N_("Schedule code for given CPU"), 0},				\
   {"debug=", &rs6000_debug_name, N_("Enable debug output"), 0},	\
   {"traceback=", &rs6000_traceback_name,				\
    N_("Select full, part, or no traceback table"), 0},			\
   {"abi=", &rs6000_abi_string, N_("Specify ABI to use"), 0},		\
   {"long-double-", &rs6000_long_double_size_string,			\
    N_("Specify size of long double (64 or 128 bits)"), 0},		\
   {"isel=", &rs6000_isel_string,                                       \
    N_("Specify yes/no if isel instructions should be generated"), 0},  \
   {"spe=", &rs6000_spe_string,                                         \
    N_("Specify yes/no if SPE SIMD instructions should be generated"), 0},\
   {"float-gprs=", &rs6000_float_gprs_string,                           \
    N_("Specify yes/no if using floating point in the GPRs"), 0},       \
   {"vrsave=", &rs6000_altivec_vrsave_string,                           \
    N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec"), 0}, \
   {"longcall", &rs6000_longcall_switch,				\
    N_("Avoid all range limits on call instructions"), 0},		\
   {"no-longcall", &rs6000_longcall_switch, "", 0},			\
   /* APPLE LOCAL begin long-branch  */					\
   {"long-branch", &rs6000_longcall_switch,				\
    N_("Avoid all range limits on call instructions"), 0},		\
   {"no-long-branch", &rs6000_longcall_switch, "", 0},			\
   /* APPLE LOCAL end long-branch  */					\
   {"warn-altivec-long", &rs6000_warn_altivec_long_switch, \
    N_("Warn about deprecated 'vector long ...' AltiVec type usage"), 0}, \
   {"no-warn-altivec-long", &rs6000_warn_altivec_long_switch, "", 0}, \
   {"sched-costly-dep=", &rs6000_sched_costly_dep_str,                  \
    N_("Determine which dependences between insns are considered costly"), 0}, \
   {"insert-sched-nops=", &rs6000_sched_insert_nops_str,                \
    N_("Specify which post scheduling nop insertion scheme to apply"), 0}, \
   {"align-", &rs6000_alignment_string,					\
    N_("Specify alignment of structure fields default/natural"), 0},	\
   {"prioritize-restricted-insns=", &rs6000_sched_restricted_insns_priority_str, \
    N_("Specify scheduling priority for dispatch slot restricted insns"), 0}, \
   /* APPLE LOCAL begin AltiVec */					\
   {"pim-altivec", &rs6000_altivec_pim_switch, \
    N_("Enable use of Motorola AltiVec PIM operations and predicates"), 0}, \
   {"no-pim-altivec", &rs6000_altivec_pim_switch, "", 0}, \
   /* APPLE LOCAL end AltiVec */					\
   SUBTARGET_OPTIONS							\
}

/* Support for a compile-time default CPU, et cetera.  The rules are:
   --with-cpu is ignored if -mcpu is specified.
   --with-tune is ignored if -mtune is specified.
   --with-float is ignored if -mhard-float or -msoft-float are
    specified.  */
#define OPTION_DEFAULT_SPECS \
  {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }

/* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
struct rs6000_cpu_select
{
  const char *string;
  const char *name;
  int set_tune_p;
  int set_arch_p;
};

extern struct rs6000_cpu_select rs6000_select[];

/* Debug support */
extern const char *rs6000_debug_name;	/* Name for -mdebug-xxxx option */
extern const char *rs6000_abi_string;	/* for -mabi={sysv,darwin,eabi,aix,altivec} */
extern int rs6000_debug_stack;		/* debug stack applications */
extern int rs6000_debug_arg;		/* debug argument handling */

#define	TARGET_DEBUG_STACK	rs6000_debug_stack
#define	TARGET_DEBUG_ARG	rs6000_debug_arg

extern const char *rs6000_traceback_name; /* Type of traceback table.  */

/* These are separate from target_flags because we've run out of bits
   there.  */
extern const char *rs6000_long_double_size_string;
extern int rs6000_long_double_type_size;
extern int rs6000_altivec_abi;
extern int rs6000_spe_abi;
extern int rs6000_isel;
extern int rs6000_spe;
extern int rs6000_float_gprs;
extern const char *rs6000_float_gprs_string;
extern const char *rs6000_isel_string;
extern const char *rs6000_spe_string;
extern const char *rs6000_altivec_vrsave_string;
extern int rs6000_altivec_vrsave;
extern const char *rs6000_longcall_switch;
extern int rs6000_default_long_calls;
extern const char* rs6000_alignment_string;
extern int rs6000_alignment_flags;
extern const char *rs6000_sched_restricted_insns_priority_str;
extern int rs6000_sched_restricted_insns_priority;
extern const char *rs6000_sched_costly_dep_str;
extern enum rs6000_dependence_cost rs6000_sched_costly_dep;
extern const char *rs6000_sched_insert_nops_str;
extern enum rs6000_nop_insertion rs6000_sched_insert_nops;

extern int rs6000_warn_altivec_long;
extern const char *rs6000_warn_altivec_long_switch;
/* APPLE LOCAL begin AltiVec */
extern int rs6000_altivec_pim;
extern const char *rs6000_altivec_pim_switch;
/* APPLE LOCAL end AltiVec */

/* Alignment options for fields in structures for sub-targets following
   AIX-like ABI.
   ALIGN_POWER word-aligns FP doubles (default AIX ABI).
   ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).

   Override the macro definitions when compiling libobjc to avoid undefined
   reference to rs6000_alignment_flags due to library's use of GCC alignment
   macros which use the macros below.  */

#ifndef IN_TARGET_LIBS
#define MASK_ALIGN_POWER   0x00000000
#define MASK_ALIGN_NATURAL 0x00000001
#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
/* APPLE LOCAL begin Macintosh alignment 2002-2-26 --ff */
#define MASK_ALIGN_MAC68K  0x00000002
#define TARGET_ALIGN_MAC68K (rs6000_alignment_flags & MASK_ALIGN_MAC68K)
/* APPLE LOCAL end Macintosh alignment 2002-2-26 --ff */
#else
#define TARGET_ALIGN_NATURAL 0
#endif

#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave

#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_E500 0
#define TARGET_ISEL 0
#define TARGET_FPRS 1
#define TARGET_E500_SINGLE 0
#define TARGET_E500_DOUBLE 0

/* Sometimes certain combinations of command options do not make sense
   on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.

   Do not use this macro to turn on various extra optimizations for
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.

   On the RS/6000 this is used to define the target cpu type.  */

#define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)

/* Define this to change the optimizations performed by default.  */
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)

/* Show we can debug even without a frame pointer.  */
#define CAN_DEBUG_WITHOUT_FP

/* Target pragma.  */
#define REGISTER_TARGET_PRAGMAS() do {				\
  c_register_pragma (0, "longcall", rs6000_pragma_longcall);	\
} while (0)

/* Target #defines.  */
#define TARGET_CPU_CPP_BUILTINS() \
  rs6000_cpu_cpp_builtins (pfile)

/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
   we're compiling for.  Some configurations may need to override it.  */
#define RS6000_CPU_CPP_ENDIAN_BUILTINS()	\
  do						\
    {						\
      if (BYTES_BIG_ENDIAN)			\
	{					\
	  builtin_define ("__BIG_ENDIAN__");	\
	  builtin_define ("_BIG_ENDIAN");	\
	  builtin_assert ("machine=bigendian");	\
	}					\
      else					\
	{					\
	  builtin_define ("__LITTLE_ENDIAN__");	\
	  builtin_define ("_LITTLE_ENDIAN");	\
	  builtin_assert ("machine=littleendian"); \
	}					\
    }						\
  while (0)

/* Target machine storage layout.  */

/* Define this macro if it is advisable to hold scalars in registers
   in a wider mode than that declared by the program.  In such cases,
   the value is constrained to be within the bounds of the declared
   type, but kept valid in the wider mode.  The signedness of the
   extension may differ from that of the type.  */

#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE)	\
  if (GET_MODE_CLASS (MODE) == MODE_INT		\
      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
    (MODE) = TARGET_32BIT ? SImode : DImode;

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
/* That is true on RS/6000.  */
#define BITS_BIG_ENDIAN 1

/* Define this if most significant byte of a word is the lowest numbered.  */
/* That is true on RS/6000.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is lowest
   numbered.

   For RS/6000 we can decide arbitrarily since there are no machine
   instructions for them.  Might as well be consistent with bits and bytes.  */
#define WORDS_BIG_ENDIAN 1

#define MAX_BITS_PER_WORD 64

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
#ifdef IN_LIBGCC2
#define MIN_UNITS_PER_WORD UNITS_PER_WORD
#else
#define MIN_UNITS_PER_WORD 4
#endif
#define UNITS_PER_FP_WORD 8
#define UNITS_PER_ALTIVEC_WORD 16
#define UNITS_PER_SPE_WORD 8

/* Type used for ptrdiff_t, as a string used in a declaration.  */