rs6000.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

/* Definitions of target machine for GNU compiler, for IBM RS/6000.
   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   Contributed by Richard Kenner ([e-mail])

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 2, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING.  If not, write to the
   Free Software Foundation, 59 Temple Place - Suite 330, Boston,
   MA 02111-1307, USA.  */

/* Note that some other tm.h files include this one and then override
   many of the definitions.  */

/* Definitions for the object file format.  These are set at
   compile-time.  */

#define OBJECT_XCOFF 1
#define OBJECT_ELF 2
#define OBJECT_PEF 3
#define OBJECT_MACHO 4

#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)

#ifndef TARGET_AIX
#define TARGET_AIX 0
#endif

/* Control whether function entry points use a "dot" symbol when
   ABI_AIX.  */
#define DOT_SYMBOLS 1

/* Default string to use for cpu if not specified.  */
#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT ((char *)0)
#endif

/* Common ASM definitions used by ASM_SPEC among the various targets
   for handling -mcpu=xxx switches.  */
#define ASM_CPU_SPEC \
"%{!mcpu*: \
  %{mpower: %{!mpower2: -mpwr}} \
  %{mpower2: -mpwrx} \
  %{mpowerpc64*: -mppc64} \
  %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
  %{mno-power: %{!mpowerpc*: -mcom}} \
  %{!mno-power: %{!mpower*: %(asm_default)}}} \
%{mcpu=common: -mcom} \
%{mcpu=power: -mpwr} \
%{mcpu=power2: -mpwrx} \
%{mcpu=power3: -mppc64} \
%{mcpu=power4: -mpower4} \
%{mcpu=power5: -mpower4} \
%{mcpu=powerpc: -mppc} \
%{mcpu=rios: -mpwr} \
%{mcpu=rios1: -mpwr} \
%{mcpu=rios2: -mpwrx} \
%{mcpu=rsc: -mpwr} \
%{mcpu=rsc1: -mpwr} \
%{mcpu=rs64a: -mppc64} \
%{mcpu=401: -mppc} \
%{mcpu=403: -m403} \
%{mcpu=405: -m405} \
%{mcpu=405fp: -m405} \
%{mcpu=440: -m440} \
%{mcpu=440fp: -m440} \
%{mcpu=505: -mppc} \
%{mcpu=601: -m601} \
%{mcpu=602: -mppc} \
%{mcpu=603: -mppc} \
%{mcpu=603e: -mppc} \
%{mcpu=ec603e: -mppc} \
%{mcpu=604: -mppc} \
%{mcpu=604e: -mppc} \
%{mcpu=620: -mppc64} \
%{mcpu=630: -mppc64} \
%{mcpu=740: -mppc} \
%{mcpu=750: -mppc} \
%{mcpu=G3: -mppc} \
%{mcpu=7400: -mppc -maltivec} \
%{mcpu=7450: -mppc -maltivec} \
%{mcpu=G4: -mppc -maltivec} \
%{mcpu=801: -mppc} \
%{mcpu=821: -mppc} \
%{mcpu=823: -mppc} \
%{mcpu=860: -mppc} \
%{mcpu=970: -mpower4 -maltivec} \
%{mcpu=G5: -mpower4 -maltivec} \
%{mcpu=8540: -me500} \
%{maltivec: -maltivec} \
-many"

#define CPP_DEFAULT_SPEC ""

#define ASM_DEFAULT_SPEC ""

/* This macro defines names of additional specifications to put in the specs
   that can be used in various specifications like CC1_SPEC.  Its definition
   is an initializer with a subgrouping for each command option.

   Each subgrouping contains a string constant, that defines the
   specification name, and a string constant that used by the GCC driver
   program.

   Do not define this macro if it does not need to do anything.  */

#define SUBTARGET_EXTRA_SPECS

#define EXTRA_SPECS							\
  { "cpp_default",		CPP_DEFAULT_SPEC },			\
  { "asm_cpu",			ASM_CPU_SPEC },				\
  { "asm_default",		ASM_DEFAULT_SPEC },			\
  SUBTARGET_EXTRA_SPECS

/* Architecture type.  */

extern int target_flags;

/* Use POWER architecture instructions and MQ register.  */
#define MASK_POWER		0x00000001

/* Use POWER2 extensions to POWER architecture.  */
#define MASK_POWER2		0x00000002

/* Use PowerPC architecture instructions.  */
#define MASK_POWERPC		0x00000004

/* Use PowerPC General Purpose group optional instructions, e.g. fsqrt.  */
#define MASK_PPC_GPOPT		0x00000008

/* Use PowerPC Graphics group optional instructions, e.g. fsel.  */
#define MASK_PPC_GFXOPT		0x00000010

/* Use PowerPC-64 architecture instructions.  */
#define MASK_POWERPC64		0x00000020

/* Use revised mnemonic names defined for PowerPC architecture.  */
#define MASK_NEW_MNEMONICS	0x00000040

/* Disable placing fp constants in the TOC; can be turned on when the
   TOC overflows.  */
#define MASK_NO_FP_IN_TOC	0x00000080

/* Disable placing symbol+offset constants in the TOC; can be turned on when
   the TOC overflows.  */
#define MASK_NO_SUM_IN_TOC	0x00000100

/* Output only one TOC entry per module.  Normally linking fails if
   there are more than 16K unique variables/constants in an executable.  With
   this option, linking fails only if there are more than 16K modules, or
   if there are more than 16K unique variables/constant in a single module.

   This is at the cost of having 2 extra loads and one extra store per
   function, and one less allocable register.  */
#define MASK_MINIMAL_TOC	0x00000200

/* Nonzero for the 64 bit ABIs: longs and pointers are 64 bits.  The
   chip is running in "64-bit mode", in which CR0 is set in dot
   operations based on all 64 bits of the register, bdnz works on 64-bit
   ctr, lr is 64 bits, and so on.  Requires MASK_POWERPC64.  */
#define MASK_64BIT		0x00000400

/* Disable use of FPRs.  */
#define MASK_SOFT_FLOAT		0x00000800

/* Enable load/store multiple, even on PowerPC */
#define MASK_MULTIPLE		0x00001000

/* Use string instructions for block moves */
#define MASK_STRING		0x00002000

/* Disable update form of load/store */
#define MASK_NO_UPDATE		0x00004000

/* Disable fused multiply/add operations */
#define MASK_NO_FUSED_MADD	0x00008000

/* Nonzero if we need to schedule the prolog and epilog.  */
#define MASK_SCHED_PROLOG	0x00010000

/* Use AltiVec instructions.  */
#define MASK_ALTIVEC		0x00020000

/* Return small structures in memory (as the AIX ABI requires).  */
#define MASK_AIX_STRUCT_RET	0x00040000

/* Use single field mfcr instruction.  */
#define MASK_MFCRF		0x00080000

/* The only remaining free bits are 0x00600000.  linux64.h uses
   0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000.
   0x80000000 is not available because target_flags is signed.  */

/* APPLE LOCAL begin long-branch  */
/* gen call addr in register for >64M range */
#define MASK_LONG_BRANCH	0x00200000
/* APPLE LOCAL end long-branch  */

/* APPLE LOCAL begin radar 4161346 */
#define MASK_PIM_ALTIVEC 0x00400000
/* APPLE LOCAL end radar 4161346 */
#define TARGET_POWER		(target_flags & MASK_POWER)
#define TARGET_POWER2		(target_flags & MASK_POWER2)
#define TARGET_POWERPC		(target_flags & MASK_POWERPC)
#define TARGET_PPC_GPOPT	(target_flags & MASK_PPC_GPOPT)
#define TARGET_PPC_GFXOPT	(target_flags & MASK_PPC_GFXOPT)
#define TARGET_NEW_MNEMONICS	(target_flags & MASK_NEW_MNEMONICS)
#define TARGET_NO_FP_IN_TOC	(target_flags & MASK_NO_FP_IN_TOC)
#define TARGET_NO_SUM_IN_TOC	(target_flags & MASK_NO_SUM_IN_TOC)
#define TARGET_MINIMAL_TOC	(target_flags & MASK_MINIMAL_TOC)
#define TARGET_64BIT		(target_flags & MASK_64BIT)
#define TARGET_SOFT_FLOAT	(target_flags & MASK_SOFT_FLOAT)
#define TARGET_MULTIPLE		(target_flags & MASK_MULTIPLE)
#define TARGET_STRING		(target_flags & MASK_STRING)
#define TARGET_NO_UPDATE	(target_flags & MASK_NO_UPDATE)
#define TARGET_NO_FUSED_MADD	(target_flags & MASK_NO_FUSED_MADD)
#define TARGET_SCHED_PROLOG	(target_flags & MASK_SCHED_PROLOG)
#define TARGET_ALTIVEC		(target_flags & MASK_ALTIVEC)
#define TARGET_AIX_STRUCT_RET	(target_flags & MASK_AIX_STRUCT_RET)
/* APPLE LOCAL long-branch  */
#define TARGET_LONG_BRANCH	(rs6000_default_long_calls)

/* Define TARGET_MFCRF if the target assembler supports the optional
   field operand for mfcr and the target processor supports the
   instruction.  */

#ifdef HAVE_AS_MFCRF
#define TARGET_MFCRF		(target_flags & MASK_MFCRF)
#else
#define TARGET_MFCRF 0
#endif


#define TARGET_32BIT		(! TARGET_64BIT)
#define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)
#define TARGET_UPDATE		(! TARGET_NO_UPDATE)
#define TARGET_FUSED_MADD	(! TARGET_NO_FUSED_MADD)

/* Emit a dtp-relative reference to a TLS variable.  */

#ifdef HAVE_AS_TLS
#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
  rs6000_output_dwarf_dtprel (FILE, SIZE, X)
#endif

#ifndef HAVE_AS_TLS
#define HAVE_AS_TLS 0
#endif

#ifdef IN_LIBGCC2
/* For libgcc2 we make sure this is a compile time constant */
#if defined (__64BIT__) || defined (__powerpc64__)
#define TARGET_POWERPC64	1
#else
#define TARGET_POWERPC64	0
#endif
#else
#define TARGET_POWERPC64	(target_flags & MASK_POWERPC64)
#endif

#define TARGET_XL_COMPAT 0

/* Run-time compilation parameters selecting different hardware subsets.

   Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES							\
 {{"power",		MASK_POWER  | MASK_MULTIPLE | MASK_STRING,	\
			N_("Use POWER instruction set")},		\
  {"power2",		(MASK_POWER | MASK_MULTIPLE | MASK_STRING	\
			 | MASK_POWER2),				\
			N_("Use POWER2 instruction set")},		\
  {"no-power2",		- MASK_POWER2,					\
			N_("Do not use POWER2 instruction set")},	\
  {"no-power",		- (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE	\
			   | MASK_STRING),				\
			N_("Do not use POWER instruction set")},	\
  {"powerpc",		MASK_POWERPC,					\
			N_("Use PowerPC instruction set")},		\
  {"no-powerpc",	- (MASK_POWERPC | MASK_PPC_GPOPT		\
			   | MASK_PPC_GFXOPT | MASK_POWERPC64),		\
			N_("Do not use PowerPC instruction set")},	\
  {"powerpc-gpopt",	MASK_POWERPC | MASK_PPC_GPOPT,			\
			N_("Use PowerPC General Purpose group optional instructions")},\
  {"no-powerpc-gpopt",	- MASK_PPC_GPOPT,				\
			N_("Do not use PowerPC General Purpose group optional instructions")},\
  {"powerpc-gfxopt",	MASK_POWERPC | MASK_PPC_GFXOPT,			\
			N_("Use PowerPC Graphics group optional instructions")},\
  {"no-powerpc-gfxopt",	- MASK_PPC_GFXOPT,				\
			N_("Do not use PowerPC Graphics group optional instructions")},\
  {"powerpc64",		MASK_POWERPC64,					\
			N_("Use PowerPC-64 instruction set")},		\
  {"no-powerpc64",	- MASK_POWERPC64,				\
			N_("Do not use PowerPC-64 instruction set")},	\
  {"altivec",		MASK_ALTIVEC ,					\
			N_("Use AltiVec instructions")},		\
  {"no-altivec",	- MASK_ALTIVEC ,					\
			N_("Do not use AltiVec instructions")},	\
  {"new-mnemonics",	MASK_NEW_MNEMONICS,				\
			N_("Use new mnemonics for PowerPC architecture")},\
  {"old-mnemonics",	-MASK_NEW_MNEMONICS,				\
			N_("Use old mnemonics for PowerPC architecture")},\
  {"full-toc",		- (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC	\
			   | MASK_MINIMAL_TOC),				\
			N_("Put everything in the regular TOC")},	\
  {"fp-in-toc",		- MASK_NO_FP_IN_TOC,				\
			N_("Place floating point constants in TOC")},	\
  {"no-fp-in-toc",	MASK_NO_FP_IN_TOC,				\
			N_("Do not place floating point constants in TOC")},\
  {"sum-in-toc",	- MASK_NO_SUM_IN_TOC,				\
			N_("Place symbol+offset constants in TOC")},	\
  {"no-sum-in-toc",	MASK_NO_SUM_IN_TOC,				\
			N_("Do not place symbol+offset constants in TOC")},\
  {"minimal-toc",	MASK_MINIMAL_TOC,				\
			"Use only one TOC entry per procedure"},	\
  {"minimal-toc",	- (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC),	\
			""},						\
  {"no-minimal-toc",	- MASK_MINIMAL_TOC,				\
			N_("Place variable addresses in the regular TOC")},\
  {"hard-float",	- MASK_SOFT_FLOAT,				\
			N_("Use hardware floating point")},		\
  {"soft-float",	MASK_SOFT_FLOAT,				\
			N_("Do not use hardware floating point")},	\
  {"multiple",		MASK_MULTIPLE,					\
			N_("Generate load/store multiple instructions")},	\
  {"no-multiple",	- MASK_MULTIPLE,				\
			N_("Do not generate load/store multiple instructions")},\
  {"string",		MASK_STRING,					\