i860.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;; Define the real conditional branch instructions.
;; ------------------------------------------------------------------------

(define_insn "cbranch"
  [(set (pc) (if_then_else (eq (cc0) (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "*
{
  if ((cc_prev_status.flags & CC_NEGATED) == 0)
    return \"bnc %l0\";
  else
    return \"bc %l0\";
}")

(define_insn "flipped_cbranch"
  [(set (pc) (if_then_else (ne (cc0)
			       (const_int 0))
			   (pc)
			   (label_ref (match_operand 0 "" ""))))]
  ""
  "*
{
  if ((cc_prev_status.flags & CC_NEGATED) == 0)
    return \"bnc %l0\";
  else
    return \"bc %l0\";
}")

(define_insn "inverse_cbranch"
  [(set (pc) (if_then_else (eq (cc0)
			       (const_int 0))
			   (pc)
			   (label_ref (match_operand 0 "" ""))))]
  ""
  "*
{
  if ((cc_prev_status.flags & CC_NEGATED) == 0)
    return \"bc %l0\";
  else
    return \"bnc %l0\";
}")


(define_insn "flipped_inverse_cbranch"
  [(set (pc) (if_then_else (ne (cc0)
			       (const_int 0))
			   (label_ref (match_operand 0 "" ""))
			   (pc)))]
  ""
  "*
{
  if ((cc_prev_status.flags & CC_NEGATED) == 0)
    return \"bc %l0\";
  else
    return \"bnc %l0\";
}")

;; Simple BTE/BTNE compare-and-branch insns made by combining.
;; Note that it is wrong to add similar patterns for QI or HImode
;; because bte/btne always compare the whole register.

(define_insn ""
  [(set (pc)
        (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
			  (match_operand:SI 1 "bte_operand" "rK"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "bte %1,%0,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
			  (match_operand:SI 1 "bte_operand" "rK"))
		      (label_ref (match_operand 2 "" ""))
		      (pc)))]
  ""
  "btne %1,%0,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (eq (match_operand:SI 0 "register_operand" "r")
			  (match_operand:SI 1 "bte_operand" "rK"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "btne %1,%0,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (match_operand:SI 0 "register_operand" "r")
			  (match_operand:SI 1 "bte_operand" "rK"))
		      (pc)
		      (label_ref (match_operand 2 "" ""))))]
  ""
  "bte %1,%0,%2")

;; Load byte/halfword, zero-extend, & compare-and-branch insns.
;; These are made by combining.

(define_insn ""
  [(set (pc)
        (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (label_ref (match_operand 2 "" ""))
                      (pc)))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.b %0,%3;bte %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (label_ref (match_operand 2 "" ""))
                      (pc)))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.b %0,%3;btne %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (pc)
                      (label_ref (match_operand 2 "" ""))))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.b %0,%3;btne %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (zero_extend:SI (match_operand:QI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (pc)
                      (label_ref (match_operand 2 "" ""))))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.b %0,%3;bte %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (label_ref (match_operand 2 "" ""))
                      (pc)))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.s %0,%3;bte %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (label_ref (match_operand 2 "" ""))
                      (pc)))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.s %0,%3;btne %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (pc)
                      (label_ref (match_operand 2 "" ""))))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.s %0,%3;btne %1,%3,%2")

(define_insn ""
  [(set (pc)
        (if_then_else (ne (zero_extend:SI (match_operand:HI 0 "memory_operand" "m"))
                          (match_operand:SI 1 "bte_operand" "K"))
                      (pc)
                      (label_ref (match_operand 2 "" ""))))
   (match_scratch:SI 3 "=r")]
  ""
  "ld.s %0,%3;bte %1,%3,%2")


;; Generation of conditionals.

;; We save the compare operands in the cmpxx patterns and use then when
;; we generate the branch.

(define_expand "cmpsi"
  [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
		       (match_operand:SI 1 "compare_operand" "")))]
  ""
  "
{ i860_compare_op0 = operands[0];
  i860_compare_op1 = operands[1];
  DONE;
}")

(define_expand "cmpsf"
  [(set (cc0) (compare (match_operand:SF 0 "register_operand" "")
		       (match_operand:SF 1 "register_operand" "")))]
  ""
  "
{ i860_compare_op0 = operands[0];
  i860_compare_op1 = operands[1];
  DONE;
}")

(define_expand "cmpdf"
  [(set (cc0) (compare (match_operand:DF 0 "register_operand" "")
		       (match_operand:DF 1 "register_operand" "")))]
  ""
  "
{ i860_compare_op0 = operands[0];
  i860_compare_op1 = operands[1];
  DONE;
}")

;; These are the standard-named conditional branch patterns.
;; Detailed comments are found in the first one only.

(define_expand "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  /* Emit a single-condition compare insn according to
     the type of operands and the condition to be tested.  */

  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
    emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == SFmode)
    emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == DFmode)
    emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1));
  else
    abort ();

  /* Emit branch-if-true.  */

  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
  DONE;
}")

(define_expand "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
    emit_insn (gen_cmpeqsi (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == SFmode)
    emit_insn (gen_cmpeqsf (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == DFmode)
    emit_insn (gen_cmpeqdf (i860_compare_op0, i860_compare_op1));
  else
    abort ();

  emit_jump_insn (gen_flipped_cbranch (operands[0]));

  DONE;
}")

(define_expand "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
    emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == SFmode)
    emit_insn (gen_cmpgtsf (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == DFmode)
    emit_insn (gen_cmpgtdf (i860_compare_op0, i860_compare_op1));
  else
    abort ();

  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
  DONE;
}")

(define_expand "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
    emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == SFmode)
    emit_insn (gen_cmpltsf (i860_compare_op0, i860_compare_op1));
  else if (GET_MODE (i860_compare_op0) == DFmode)
    emit_insn (gen_cmpltdf (i860_compare_op0, i860_compare_op1));
  else
    abort ();

  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
  DONE;
}")

(define_expand "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
    {
      emit_insn (gen_cmpgtsi (i860_compare_op0, i860_compare_op1));
      emit_jump_insn (gen_flipped_cbranch (operands[0]));
    }
  else
    {
      if (GET_MODE (i860_compare_op0) == SFmode)
	emit_insn (gen_cmplesf (i860_compare_op0, i860_compare_op1));
      else if (GET_MODE (i860_compare_op0) == DFmode)
	emit_insn (gen_cmpledf (i860_compare_op0, i860_compare_op1));
      else
	abort ();
      emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
    }
  DONE;
}")

(define_expand "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) == MODE_INT)
    {
      emit_insn (gen_cmpltsi (i860_compare_op0, i860_compare_op1));
      emit_jump_insn (gen_flipped_cbranch (operands[0]));
    }
  else
    {
      if (GET_MODE (i860_compare_op0) == SFmode)
	emit_insn (gen_cmpgesf (i860_compare_op0, i860_compare_op1));
      else if (GET_MODE (i860_compare_op0) == DFmode)
	emit_insn (gen_cmpgedf (i860_compare_op0, i860_compare_op1));
      else
	abort ();
      emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
    }
  DONE;
}")

(define_expand "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
    abort ();

  emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1));
  emit_jump_insn (gen_flipped_cbranch (operands[0]));
  DONE;
}")

(define_expand "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
    abort ();

  emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1));
  emit_jump_insn (gen_flipped_cbranch (operands[0]));
  DONE;
}")

(define_expand "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
    abort ();

  emit_insn (gen_cmpgeusi (i860_compare_op0, i860_compare_op1));
  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
  DONE;
}")

(define_expand "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "
{
  if (GET_MODE_CLASS (GET_MODE (i860_compare_op0)) != MODE_INT)
    abort ();

  emit_insn (gen_cmpleusi (i860_compare_op0, i860_compare_op1));
  emit_jump_insn (gen_flipped_inverse_cbranch (operands[0]));
  DONE;
}")

;; Move instructions

;; Note that source operands for `mov' pseudo-instructions are no longer
;; allowed (by the SVR4 assembler) to be "big" things, i.e. constants that
;; won't fit in 16-bits.  (This includes any sort of a relocatable address
;; also.)  Thus, we must use an explicit orh/or pair of instructions if
;; the source operand is something "big".

(define_insn "movsi"
  [(set (match_operand:SI 0 "general_operand" "=r,m,f")