iq2000.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

  iq2000_debugger_offset (X, (HOST_WIDE_INT) 0)

#define DEBUGGER_ARG_OFFSET(OFFSET, X)  \
  iq2000_debugger_offset (X, (HOST_WIDE_INT) OFFSET)

#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG

#define DWARF2_DEBUGGING_INFO 1


/* Miscellaneous Parameters.  */

#define PREDICATE_CODES							\
  {"uns_arith_operand",		{ REG, CONST_INT, SUBREG }},		\
  {"arith_operand",		{ REG, CONST_INT, SUBREG }},		\
  {"small_int",			{ CONST_INT }},				\
  {"large_int",			{ CONST_INT }},				\
  {"reg_or_0_operand",		{ REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
  {"simple_memory_operand",	{ MEM, SUBREG }},			\
  {"equality_op",		{ EQ, NE }},				\
  {"cmp_op",			{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
				  LTU, LEU }},				\
  {"pc_or_label_operand",	{ PC, LABEL_REF }},			\
  {"call_insn_operand",		{ CONST_INT, CONST, SYMBOL_REF, REG}},	\
  {"move_operand", 		{ CONST_INT, CONST_DOUBLE, CONST,	\
				  SYMBOL_REF, LABEL_REF, SUBREG,	\
				  REG, MEM}},				\
  {"power_of_2_operand",	{ CONST_INT }},

#define CASE_VECTOR_MODE SImode

#define WORD_REGISTER_OPERATIONS

#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND

#define MOVE_MAX 4

#define MAX_MOVE_MAX 8

#define SHIFT_COUNT_TRUNCATED 1

#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1

#define STORE_FLAG_VALUE 1

#define Pmode SImode

#define FUNCTION_MODE SImode

/* Standard GCC variables that we reference.  */

extern char	call_used_regs[];

/* IQ2000 external variables defined in iq2000.c.  */

/* Comparison type.  */
enum cmp_type
{
  CMP_SI,				/* Compare four byte integers.  */
  CMP_DI,				/* Compare eight byte integers.  */
  CMP_SF,				/* Compare single precision floats.  */
  CMP_DF,				/* Compare double precision floats.  */
  CMP_MAX				/* Max comparison type.  */
};

/* Types of delay slot.  */
enum delay_type
{
  DELAY_NONE,				/* No delay slot.  */
  DELAY_LOAD,				/* Load from memory delay.  */
  DELAY_FCMP				/* Delay after doing c.<xx>.{d,s}.  */
};

/* Which processor to schedule for.  */

enum processor_type
{
  PROCESSOR_DEFAULT,
  PROCESSOR_IQ2000,
  PROCESSOR_IQ10
};

/* Recast the cpu class to be the cpu attribute.  */
#define iq2000_cpu_attr ((enum attr_cpu) iq2000_tune)

/* Functions to change what output section we are using.  */
extern void		rdata_section (void);
extern void		sdata_section (void);
extern void		sbss_section  (void);

#define BITMASK_UPPER16	((unsigned long) 0xffff << 16)	/* 0xffff0000 */
#define BITMASK_LOWER16	((unsigned long) 0xffff)	/* 0x0000ffff */


#define GENERATE_BRANCHLIKELY  (ISA_HAS_BRANCHLIKELY)

/* Macros to decide whether certain features are available or not,
   depending on the instruction set architecture level.  */

#define BRANCH_LIKELY_P()	GENERATE_BRANCHLIKELY

/* ISA has branch likely instructions.  */
#define ISA_HAS_BRANCHLIKELY	(iq2000_isa == 1)


#undef ASM_SPEC


/* The mapping from gcc register number to DWARF 2 CFA column number.  */
#define DWARF_FRAME_REGNUM(REG)        (REG)

/* The DWARF 2 CFA column which tracks the return address.  */
#define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)

/* Describe how we implement __builtin_eh_return.  */
#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)

/* The EH_RETURN_STACKADJ_RTX macro returns RTL which describes the
   location used to store the amount to adjust the stack.  This is
   usually a register that is available from end of the function's body
   to the end of the epilogue. Thus, this cannot be a register used as a
   temporary by the epilogue.

   This must be an integer register.  */
#define EH_RETURN_STACKADJ_REGNO        3
#define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)

/* The EH_RETURN_HANDLER_RTX macro returns RTL which describes the
   location used to store the address the processor should jump to
   catch exception.  This is usually a registers that is available from
   end of the function's body to the end of the epilogue. Thus, this
   cannot be a register used as a temporary by the epilogue.

   This must be an address register.  */
#define EH_RETURN_HANDLER_REGNO         26
#define EH_RETURN_HANDLER_RTX           \
        gen_rtx_REG (Pmode, EH_RETURN_HANDLER_REGNO)

/* Offsets recorded in opcodes are a multiple of this alignment factor.  */
#define DWARF_CIE_DATA_ALIGNMENT 4

/* For IQ2000, width of a floating point register.  */
#define UNITS_PER_FPREG 4

/* Force right-alignment for small varargs in 32 bit little_endian mode */

#define PAD_VARARGS_DOWN !BYTES_BIG_ENDIAN

/* Internal macros to classify a register number as to whether it's a
   general purpose register, a floating point register, a
   multiply/divide register, or a status register.  */

#define GP_REG_FIRST 0
#define GP_REG_LAST  31
#define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)

#define RAP_REG_NUM   32
#define AT_REGNUM	(GP_REG_FIRST + 1)

#define GP_REG_P(REGNO)	\
  ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)

/* IQ2000 registers used in prologue/epilogue code when the stack frame
   is larger than 32K bytes.  These registers must come from the
   scratch register set, and not used for passing and returning
   arguments and any other information used in the calling sequence.  */

#define IQ2000_TEMP1_REGNUM (GP_REG_FIRST + 12)
#define IQ2000_TEMP2_REGNUM (GP_REG_FIRST + 13)

/* This macro is used later on in the file.  */
#define GR_REG_CLASS_P(CLASS)						\
  ((CLASS) == GR_REGS)

#define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
#define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)

/* Certain machines have the property that some registers cannot be
   copied to some other registers without using memory.  Define this
   macro on those machines to be a C expression that is nonzero if
   objects of mode MODE in registers of CLASS1 can only be copied to
   registers of class CLASS2 by storing a register of CLASS1 into
   memory and loading that memory location into a register of CLASS2.

   Do not define this macro if its value would always be zero.  */

/* Return the maximum number of consecutive registers
   needed to represent mode MODE in a register of class CLASS.  */

#define CLASS_UNITS(mode, size)						\
  ((GET_MODE_SIZE (mode) + (size) - 1) / (size))

/* If defined, gives a class of registers that cannot be used as the
   operand of a SUBREG that changes the mode of the object illegally.  */

#define CLASS_CANNOT_CHANGE_MODE 0

/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE.  */

#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
  (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))

/* Make sure 4 words are always allocated on the stack.  */

#ifndef STACK_ARGS_ADJUST
#define STACK_ARGS_ADJUST(SIZE)						\
  {									\
    if (SIZE.constant < 4 * UNITS_PER_WORD)				\
      SIZE.constant = 4 * UNITS_PER_WORD;				\
  }
#endif


/* Symbolic macros for the registers used to return integer and floating
   point values.  */

#define GP_RETURN (GP_REG_FIRST + 2)

/* Symbolic macros for the first/last argument registers.  */

#define GP_ARG_FIRST (GP_REG_FIRST + 4)
#define GP_ARG_LAST  (GP_REG_FIRST + 11)

#define MAX_ARGS_IN_REGISTERS	8


/* Tell prologue and epilogue if register REGNO should be saved / restored.  */

#define MUST_SAVE_REGISTER(regno) \
 ((regs_ever_live[regno] && !call_used_regs[regno])			\
  || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)	\
  || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))

/* ALIGN FRAMES on double word boundaries */
#ifndef IQ2000_STACK_ALIGN
#define IQ2000_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
#endif


/* These assume that REGNO is a hard or pseudo reg number.
   They give nonzero only if REGNO is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   These definitions are NOT overridden anywhere.  */

#define BASE_REG_P(regno, mode)					\
  (GP_REG_P (regno))

#define GP_REG_OR_PSEUDO_STRICT_P(regno, mode)				    \
  BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
	     (mode))

#define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
  (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))

#define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
  GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects them all.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Some source files that are used after register allocation
   need to be strict.  */

#ifndef REG_OK_STRICT
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
  iq2000_reg_mode_ok_for_base_p (X, MODE, 0)
#else
#define REG_MODE_OK_FOR_BASE_P(X, MODE) \
  iq2000_reg_mode_ok_for_base_p (X, MODE, 1)
#endif

#if 1
#define GO_PRINTF(x)	fprintf (stderr, (x))
#define GO_PRINTF2(x,y)	fprintf (stderr, (x), (y))
#define GO_DEBUG_RTX(x) debug_rtx (x)

#else
#define GO_PRINTF(x)
#define GO_PRINTF2(x,y)
#define GO_DEBUG_RTX(x)
#endif

/* If defined, modifies the length assigned to instruction INSN as a
   function of the context in which it is used.  LENGTH is an lvalue
   that contains the initially computed length of the insn and should
   be updated with the correct length of the insn.  */
#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  ((LENGTH) = iq2000_adjust_insn_length ((INSN), (LENGTH)))


/* A list of predicates that do special things with modes, and so
   should not elicit warnings for VOIDmode match_operand.  */

#define SPECIAL_MODE_PREDICATES \
  "pc_or_label_operand",




/* How to tell the debugger about changes of source files.  */

#ifndef SET_FILE_NUMBER
#define SET_FILE_NUMBER() ++ num_source_filenames
#endif

/* This is how to output a note the debugger telling it the line number
   to which the following sequence of instructions corresponds.  */

#ifndef LABEL_AFTER_LOC
#define LABEL_AFTER_LOC(STREAM)
#endif


/* Default to -G 8 */
#ifndef IQ2000_DEFAULT_GVALUE
#define IQ2000_DEFAULT_GVALUE 8
#endif

#define SDATA_SECTION_ASM_OP	"\t.sdata"	/* Small data.  */


/* See iq2000_expand_prologue's use of loadgp for when this should be
   true.  */

#define DONT_ACCESS_GBLS_AFTER_EPILOGUE 0

/* List of all IQ2000 punctuation characters used by print_operand.  */
extern char iq2000_print_operand_punct[256];

/* The target cpu for optimization and scheduling.  */
extern enum processor_type iq2000_tune;

/* Which instruction set architecture to use.  */
extern int iq2000_isa;

/* Cached operands, and operator to compare for use in set/branch/trap
   on condition codes.  */
extern rtx branch_cmp[2];

/* What type of branch to use.  */
extern enum cmp_type branch_type;

/* Strings to hold which cpu and instruction set architecture to use.  */
extern const char * iq2000_cpu_string;	  /* For -mcpu=<xxx>.  */
extern const char * iq2000_arch_string;   /* For -march=<xxx>.  */



enum iq2000_builtins
{
  IQ2000_BUILTIN_ADO16,
  IQ2000_BUILTIN_CFC0,
  IQ2000_BUILTIN_CFC1,
  IQ2000_BUILTIN_CFC2,
  IQ2000_BUILTIN_CFC3,
  IQ2000_BUILTIN_CHKHDR,
  IQ2000_BUILTIN_CTC0,
  IQ2000_BUILTIN_CTC1,
  IQ2000_BUILTIN_CTC2,
  IQ2000_BUILTIN_CTC3,
  IQ2000_BUILTIN_LU,
  IQ2000_BUILTIN_LUC32L,
  IQ2000_BUILTIN_LUC64,
  IQ2000_BUILTIN_LUC64L,
  IQ2000_BUILTIN_LUK,
  IQ2000_BUILTIN_LULCK,
  IQ2000_BUILTIN_LUM32,
  IQ2000_BUILTIN_LUM32L,
  IQ2000_BUILTIN_LUM64,
  IQ2000_BUILTIN_LUM64L,
  IQ2000_BUILTIN_LUR,
  IQ2000_BUILTIN_LURL,
  IQ2000_BUILTIN_MFC0,
  IQ2000_BUILTIN_MFC1,
  IQ2000_BUILTIN_MFC2,
  IQ2000_BUILTIN_MFC3,
  IQ2000_BUILTIN_MRGB,
  IQ2000_BUILTIN_MTC0,
  IQ2000_BUILTIN_MTC1,
  IQ2000_BUILTIN_MTC2,
  IQ2000_BUILTIN_MTC3,
  IQ2000_BUILTIN_PKRL,
  IQ2000_BUILTIN_RAM,
  IQ2000_BUILTIN_RB,
  IQ2000_BUILTIN_RX,
  IQ2000_BUILTIN_SRRD,
  IQ2000_BUILTIN_SRRDL,
  IQ2000_BUILTIN_SRULC,
  IQ2000_BUILTIN_SRULCK,
  IQ2000_BUILTIN_SRWR,
  IQ2000_BUILTIN_SRWRU,
  IQ2000_BUILTIN_TRAPQF,
  IQ2000_BUILTIN_TRAPQFL,
  IQ2000_BUILTIN_TRAPQN,
  IQ2000_BUILTIN_TRAPQNE,
  IQ2000_BUILTIN_TRAPRE,
  IQ2000_BUILTIN_TRAPREL,
  IQ2000_BUILTIN_WB,
  IQ2000_BUILTIN_WBR,
  IQ2000_BUILTIN_WBU,
  IQ2000_BUILTIN_WX,
  IQ2000_BUILTIN_SYSCALL
};