iq2000.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

			   gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
	  DONE;
	}

      /* We have a call returning a DImode structure in an FP reg.
	 Strip off the now unnecessary PARALLEL.  */
      if (GET_CODE (operands[0]) == PARALLEL)
	operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);

      emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
					        gen_rtx_REG (SImode,
							     GP_REG_FIRST + 31)));

      DONE;
    }
}")

(define_expand "call_value_internal0"
  [(parallel [(set (match_operand 0 "" "")
		   (call (match_operand 1 "" "")
			 (match_operand 2 "" "")))
	      (clobber (match_operand:SI 3 "" ""))])]
  ""
  "")

(define_insn "call_value_internal1"
  [(set (match_operand 0 "register_operand" "=df")
        (call (mem (match_operand 1 "call_insn_operand" "ri"))
              (match_operand 2 "" "i")))
   (clobber (match_operand:SI 3 "register_operand" "=d"))]
  ""
  "*
{
  register rtx target = operands[1];

  if (GET_CODE (target) == CONST_INT)
    return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
  else if (CONSTANT_ADDRESS_P (target))
    return \"jal\\t%1\";
  else
    return \"jalr\\t%3,%1\";
}"
  [(set_attr "type"	"call")
   (set_attr "mode"	"none")])

(define_expand "call_value_multiple_internal0"
  [(parallel [(set (match_operand 0 "" "")
		   (call (match_operand 1 "" "")
			 (match_operand 2 "" "")))
	      (set (match_operand 3 "" "")
		   (call (match_dup 1)
			 (match_dup 2)))
	      (clobber (match_operand:SI 4 "" ""))])]
  ""
  "")

;; ??? May eventually need all 6 versions of the call patterns with multiple
;; return values.

(define_insn "call_value_multiple_internal1"
  [(set (match_operand 0 "register_operand" "=df")
        (call (mem (match_operand 1 "call_insn_operand" "ri"))
              (match_operand 2 "" "i")))
   (set (match_operand 3 "register_operand" "=df")
   	(call (mem (match_dup 1))
              (match_dup 2)))
  (clobber (match_operand:SI 4 "register_operand" "=d"))]
  ""
  "*
{
  register rtx target = operands[1];

  if (GET_CODE (target) == CONST_INT)
    return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
  else if (CONSTANT_ADDRESS_P (target))
    return \"jal\\t%1\";
  else
    return \"jalr\\t%4,%1\";
}"
  [(set_attr "type"	"call")
   (set_attr "mode"	"none")])

;; Call subroutine returning any type.

(define_expand "untyped_call"
  [(parallel [(call (match_operand 0 "" "")
		    (const_int 0))
	      (match_operand 1 "" "")
	      (match_operand 2 "" "")])]
  ""
  "
{
  if (operands[0])		/* silence statement not reached warnings */
    {
      int i;

      emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));

      for (i = 0; i < XVECLEN (operands[2], 0); i++)
	{
	  rtx set = XVECEXP (operands[2], 0, i);
	  emit_move_insn (SET_DEST (set), SET_SRC (set));
	}

      emit_insn (gen_blockage ());
      DONE;
    }
}")

;;
;;  ....................
;;
;;	MISC.
;;
;;  ....................
;;

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop"
  [(set_attr "type"	"nop")
   (set_attr "mode"	"none")])


;; For the rare case where we need to load an address into a register
;; that cannot be recognized by the normal movsi/addsi instructions.
;; I have no idea how many insns this can actually generate.  It should
;; be rare, so over-estimating as 10 instructions should not have any
;; real performance impact.
(define_insn "leasi"
  [(set (match_operand:SI 0 "register_operand" "=d")
        (match_operand:SI 1 "address_operand" "p"))]
  "Pmode == SImode"
  "*
{
  rtx xoperands [3];

  xoperands[0] = operands[0];
  xoperands[1] = XEXP (operands[1], 0);
  xoperands[2] = XEXP (operands[1], 1);
  output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands);
  return \"\";
}"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")
   (set_attr "length"	"40")])

(define_insn "ado16"
  [(set (match_operand:SI             0 "register_operand" "=r")
	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
		    (match_operand:SI 2 "register_operand" "r")]
		UNSPEC_ADO16))]
  ""
  "ado16\\t%0, %1, %2"
)

(define_insn "ram"
  [(set (match_operand:SI             0 "register_operand" "=r")
	      (unspec:SI [(match_operand:SI 1 "register_operand" "r")
		                (match_operand:SI 2 "const_int_operand" "I")
		                (match_operand:SI 3 "const_int_operand" "I")
		                (match_operand:SI 4 "const_int_operand" "I")]
		     UNSPEC_RAM))]
  ""
  "ram\\t%0, %1, %2, %3, %4"
)

(define_insn "chkhdr"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_CHKHDR)]
  ""
  "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "pkrl"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_PKRL)]
  ""
  "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "cfc0"
   [(set (match_operand:SI                0 "register_operand" "=r")
    (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_CFC0))]
  ""
  "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "cfc1"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_CFC1))]
  ""
  "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "cfc2"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_CFC2))]
  ""
  "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "cfc3"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_CFC3))]
  ""
  "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "ctc0"
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_CTC0)]
  ""
  "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "ctc1"
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_CTC1)]
  ""
  "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "ctc2"
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_CTC2)]
  ""
  "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "ctc3"
  [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_CTC3)]
  ""
  "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "mfc0"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_MFC0))]
  ""
  "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "mfc1"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_MFC1))]
  ""
  "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "mfc2"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_MFC2))]
  ""
  "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "mfc3"
   [(set (match_operand:SI                0 "register_operand" "=r")
   (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")]
 		UNSPEC_MFC3))]
  ""
  "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "mtc0"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_MTC0)]
  ""
  "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "mtc1"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_MTC1)]
  ""
  "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "mtc2"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_MTC2)]
  ""
  "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "mtc3"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "const_int_operand" "I")]
		UNSPEC_MTC3)]
  ""
  "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "lur"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUR)]
  ""
  "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "rb"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_RB)]
  ""
  "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "rx"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_RX)]
  ""
  "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "srrd"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
		UNSPEC_SRRD)]
  ""
  "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "srwr"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_SRWR)]
  ""
  "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "wb"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_WB)]
  ""
  "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "wx"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_WX)]
  ""
  "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "luc32"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUC32)]
  ""
  "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "luc32l"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUC32L)]
  ""
  "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "luc64"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUC64)]
  ""
  "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "luc64l"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUC64L)]
  ""
  "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "luk"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUK)]
  ""
  "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"ok_in_dslot")]
)

(define_insn "lulck"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
		UNSPEC_LULCK)]
  ""
  "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "lum32"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUM32)]
  ""
  "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "lum32l"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUM32L)]
  ""
  "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);" 
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "lum64"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUM64)]
  ""
  "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "lum64l"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LUM64L)]
  ""
  "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "lurl"
  [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")
		(match_operand:SI 1 "register_operand" "r")]
		UNSPEC_LURL)]
  ""
  "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);"
  [(set_attr "dslot"	"not_in_dslot")]
)

(define_insn "mrgb"
  [(set (match_operand:SI                 0 "register_operand" "=r")
  	(unspec_volatile:SI [(match_operand:SI 1 "r