iq2000.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;;  iq2000.md	     Machine Description for Vitesse IQ2000 processors
;;  Copyright (C) 2003, 2004 Free Software Foundation, Inc.

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.

;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING.  If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.

(define_constants
  [(UNSPEC_ADO16 0)
   (UNSPEC_RAM	1)
   (UNSPEC_CHKHDR 2)
   (UNSPEC_PKRL	3)
   (UNSPEC_CFC0	4)
   (UNSPEC_CFC1	5)
   (UNSPEC_CFC2	6)
   (UNSPEC_CFC3	7)
   (UNSPEC_CTC0	8)
   (UNSPEC_CTC1	9)
   (UNSPEC_CTC2	10)
   (UNSPEC_CTC3	11)
   (UNSPEC_MFC0	12)
   (UNSPEC_MFC1	13)
   (UNSPEC_MFC2	14)
   (UNSPEC_MFC3	15)
   (UNSPEC_MTC0	16)
   (UNSPEC_MTC1	17)
   (UNSPEC_MTC2	18)
   (UNSPEC_MTC3	19)
   (UNSPEC_LUR	20)
   (UNSPEC_RB	21)
   (UNSPEC_RX	22)
   (UNSPEC_SRRD	23)
   (UNSPEC_SRWR	24)
   (UNSPEC_WB	25)
   (UNSPEC_WX	26)
   (UNSPEC_LUC32 49)
   (UNSPEC_LUC32L 27)
   (UNSPEC_LUC64 28)
   (UNSPEC_LUC64L 29)
   (UNSPEC_LUK 30)
   (UNSPEC_LULCK 31)
   (UNSPEC_LUM32 32)
   (UNSPEC_LUM32L 33)
   (UNSPEC_LUM64 34)
   (UNSPEC_LUM64L 35)
   (UNSPEC_LURL 36)
   (UNSPEC_MRGB 37)
   (UNSPEC_SRRDL 38)
   (UNSPEC_SRULCK 39)
   (UNSPEC_SRWRU 40)
   (UNSPEC_TRAPQFL 41)
   (UNSPEC_TRAPQNE 42)
   (UNSPEC_TRAPREL 43)
   (UNSPEC_WBU 44)
   (UNSPEC_SYSCALL 45)]
)
;; UNSPEC values used in iq2000.md
;; Number	USE
;; 0		movsi_ul
;; 1		movsi_us, get_fnaddr
;; 3		eh_set_return
;; 20		builtin_setjmp_setup
;;
;; UNSPEC_VOLATILE values
;; 0		blockage
;; 2		loadgp
;; 3		builtin_longjmp
;; 4		exception_receiver
;; 10		consttable_qi
;; 11		consttable_hi
;; 12		consttable_si
;; 13		consttable_di
;; 14		consttable_sf
;; 15		consttable_df
;; 16		align_2
;; 17		align_4
;; 18		align_8


;; ....................
;;
;;	Attributes
;;
;; ....................

;; Classification of each insn.
;; branch	conditional branch
;; jump		unconditional jump
;; call		unconditional call
;; load		load instruction(s)
;; store	store instruction(s)
;; move		data movement within same register set
;; xfer		transfer to/from coprocessor
;; arith	integer arithmetic instruction
;; darith	double precision integer arithmetic instructions
;; imul		integer multiply
;; idiv		integer divide
;; icmp		integer compare
;; fadd		floating point add/subtract
;; fmul		floating point multiply
;; fmadd	floating point multiply-add
;; fdiv		floating point divide
;; fabs		floating point absolute value
;; fneg		floating point negation
;; fcmp		floating point compare
;; fcvt		floating point convert
;; fsqrt	floating point square root
;; multi	multiword sequence (or user asm statements)
;; nop		no operation

(define_attr "type"
  "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
  (const_string "unknown"))

;; Main data type used by the insn
(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))

;; Length (in # of bytes).  A conditional branch is allowed only to a
;; location within a signed 18-bit offset of the delay slot.  If that
;; provides too small a range, we use the `j' instruction.  This
;; instruction takes a 28-bit value, but that value is not an offset.
;; Instead, it's bitwise-ored with the high-order four bits of the
;; instruction in the delay slot, which means it cannot be used to
;; cross a 256MB boundary.  We could fall back back on the jr,
;; instruction which allows full access to the entire address space,
;; but we do not do so at present.

(define_attr "length" ""
   (cond [(eq_attr "type" "branch")
          (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
                     (const_int 131072))
                 (const_int 4)]
	         (const_int 12))]
          (const_int 4)))

(define_attr "cpu"
  "default,iq2000"
  (const (symbol_ref "iq2000_cpu_attr")))

;; Does the instruction have a mandatory delay slot? has_dslot
;; Can the instruction be in a delay slot? ok_in_dslot
;; Can the instruction not be in a delay slot? not_in_dslot
(define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot"
  (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp")
		(const_string "has_dslot")
		(const_string "ok_in_dslot")))

;; Attribute defining whether or not we can use the branch-likely instructions

(define_attr "branch_likely" "no,yes"
  (const
   (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
		 (const_string "yes")
		 (const_string "no"))))


;; Describe a user's asm statement.
(define_asm_attributes
  [(set_attr "type" "multi")])



;; .........................
;;
;;	Delay slots, can't describe load/fcmp/xfer delay slots here
;;
;; .........................

(define_delay (eq_attr "type" "jump")
  [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
   (nil)
   (nil)])

(define_delay (eq_attr "type" "branch")
  [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
   (nil)
   (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))])

(define_delay (eq_attr "type" "call")
  [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4"))
   (nil)
   (nil)])



;; .........................
;;
;;	Pipeline model
;;
;; .........................

(define_automaton "iq2000")
(define_cpu_unit "core,memory" "iq2000")

(define_insn_reservation "nonmemory" 1
  (eq_attr "type" "!load,move,store,xfer")
  "core")

(define_insn_reservation "iq2000_load_move" 3
  (and (eq_attr "type" "load,move")
       (eq_attr "cpu" "iq2000"))
  "memory")

(define_insn_reservation "other_load_move" 1
  (and (eq_attr "type" "load,move")
       (eq_attr "cpu" "!iq2000"))
  "memory")

(define_insn_reservation "store" 1
  (eq_attr "type" "store")
  "memory")

(define_insn_reservation "xfer" 2
  (eq_attr "type" "xfer")
  "memory")

;;
;;  ....................
;;
;;	CONDITIONAL TRAPS
;;
;;  ....................
;;

(define_insn "trap"
  [(trap_if (const_int 1) (const_int 0))]
  ""
  "*
{
  return \"break\";
}")

;;
;;  ....................
;;
;;	ADDITION
;;
;;  ....................
;;

(define_expand "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
		 (match_operand:SI 2 "arith_operand" "dI")))]
  ""
  "")

(define_insn "addsi3_internal"
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
		 (match_operand:SI 2 "arith_operand" "d,I")))]
  ""
  "@
   addu\\t%0,%z1,%2
   addiu\\t%0,%z1,%2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;;
;;  ....................
;;
;;	SUBTRACTION
;;
;;  ....................
;;

(define_expand "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
		  (match_operand:SI 2 "arith_operand" "dI")))]
  ""
  "")

(define_insn "subsi3_internal"
  [(set (match_operand:SI 0 "register_operand" "=d,=d")
	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")
		  (match_operand:SI 2 "arith_operand" "d,I")))]
  ""
  "@
   subu\\t%0,%z1,%2
   addiu\\t%0,%z1,%n2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;;
;;  ....................
;;
;;	NEGATION and ONE'S COMPLEMENT
;;
;;  ....................

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(neg:SI (match_operand:SI 1 "register_operand" "d")))]
  ""
  "*
{
  operands[2] = const0_rtx;
  return \"subu\\t%0,%z2,%1\";
}"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(not:SI (match_operand:SI 1 "register_operand" "d")))]
  ""
  "*
{
  operands[2] = const0_rtx;
  return \"nor\\t%0,%z2,%1\";
}"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;;
;;  ....................
;;
;;	LOGICAL
;;
;;  ....................
;;

(define_expand "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
		(match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d")
		(match_operand:SI 2 "nonmemory_operand" "d,K,N")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"and\\t%0,%1,%2\";
  else if (which_alternative == 1)
    return \"andi\\t%0,%1,%x2\";
  else if (which_alternative == 2)
    {
      if ((INTVAL (operands[2]) & 0xffff) == 0xffff)
	{
	  operands[2] = GEN_INT (INTVAL (operands[2]) >> 16);
	  return \"andoui\\t%0,%1,%x2\";
	}
      else
	{
	  operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
	  return \"andoi\\t%0,%1,%x2\";
	}
    }
}"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_expand "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "=d,d")
	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,d")
	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
  ""
  "@
   or\\t%0,%1,%2
   ori\\t%0,%1,%x2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_expand "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=d,d")
	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,d")
	(xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
  ""
  "@
   xor\\t%0,%1,%2
   xori\\t%0,%1,%x2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

(define_insn "*norsi3"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
		(not:SI (match_operand:SI 2 "register_operand" "d"))))]
  ""
  "nor\\t%0,%z1,%z2"
  [(set_attr "type"	"arith")
   (set_attr "mode"	"SI")])

;;
;;  ....................
;;
;;	ZERO EXTENSION
;;
;;  ....................

;; Extension insns.
;; Those for integer source operand are ordered widest source type first.

(define_expand "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"andi\\t%0,%1,0xffff\";
  else
    return iq2000_move_1word (operands, insn, TRUE);
}"
  [(set_attr "type"	"arith,load,load")
   (set_attr "mode"	"SI")
   (set_attr "length"	"4,4,8")])

(define_expand "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=d,d,d")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"andi\\t%0,%1,0x00ff\";
  else
    return iq2000_move_1word (operands, insn, TRUE);
}"
  [(set_attr "type"	"arith,load,load")
   (set_attr "mode"	"HI")
   (set_attr "length"	"4,4,8")])

(define_expand "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"andi\\t%0,%1,0x00ff\";
  else
    return iq2000_move_1word (operands, insn, TRUE);
}"
  [(set_attr "type"	"arith,load,load")
   (set_attr "mode"	"SI")
   (set_attr "length"	"4,4,8")])

;;
;;  ....................
;;
;;	SIGN EXTENSION
;;
;;  ....................

;; Extension insns.