pa.h

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

	  {								\
	    fputs ("\tbve	(%r21)\n", FILE);			\
	    fputs ("\tldw	40(%r22),%r29\n", FILE);		\
	    fputs ("\t.word	0\n", FILE);				\
	    fputs ("\t.word	0\n", FILE);				\
	  }								\
	else								\
	  {								\
	    fputs ("\tldsid	(%r21),%r1\n", FILE);			\
	    fputs ("\tmtsp	%r1,%sr0\n", FILE);			\
	    fputs ("\tbe	0(%sr0,%r21)\n", FILE);			\
	    fputs ("\tldw	40(%r22),%r29\n", FILE);		\
	  }								\
	fputs ("\t.word	0\n", FILE);					\
	fputs ("\t.word	0\n", FILE);					\
	fputs ("\t.word	0\n", FILE);					\
	fputs ("\t.word	0\n", FILE);					\
      }									\
    else								\
      {									\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\tmfia	%r31\n", FILE);					\
	fputs ("\tldd	24(%r31),%r1\n", FILE);				\
	fputs ("\tldd	24(%r1),%r27\n", FILE);				\
	fputs ("\tldd	16(%r1),%r1\n", FILE);				\
	fputs ("\tbve	(%r1)\n", FILE);				\
	fputs ("\tldd	32(%r31),%r31\n", FILE);			\
	fputs ("\t.dword 0  ; fptr\n", FILE);				\
	fputs ("\t.dword 0  ; static link\n", FILE);			\
      }									\
  }

/* Length in units of the trampoline for entering a nested function.  */

#define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)

/* Length in units of the trampoline instruction code.  */

#define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))

/* Minimum length of a cache line.  A length of 16 will work on all
   PA-RISC processors.  All PA 1.1 processors have a cache line of
   32 bytes.  Most but not all PA 2.0 processors have a cache line
   of 64 bytes.  As cache flushes are expensive and we don't support
   PA 1.0, we use a minimum length of 32.  */

#define MIN_CACHELINE_SIZE 32

/* Emit RTL insns to initialize the variable parts of a trampoline.
   FNADDR is an RTX for the address of the function's pure code.
   CXT is an RTX for the static chain value for the function.

   Move the function address to the trampoline template at offset 36.
   Move the static chain value to trampoline template at offset 40.
   Move the trampoline address to trampoline template at offset 44.
   Move r19 to trampoline template at offset 48.  The latter two
   words create a plabel for the indirect call to the trampoline.

   A similar sequence is used for the 64-bit port but the plabel is
   at the beginning of the trampoline.

   Finally, the cache entries for the trampoline code are flushed.
   This is necessary to ensure that the trampoline instruction sequence
   is written to memory prior to any attempts at prefetching the code
   sequence.  */

#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) 			\
{									\
  rtx start_addr = gen_reg_rtx (Pmode);					\
  rtx end_addr = gen_reg_rtx (Pmode);					\
  rtx line_length = gen_reg_rtx (Pmode);				\
  rtx tmp;								\
									\
  if (!TARGET_64BIT)							\
    {									\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 36));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR));		\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 40));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT));			\
									\
      /* Create a fat pointer for the trampoline.  */			\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 44));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP));		\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 48));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      gen_rtx_REG (Pmode, 19));				\
									\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  We align the	\
	 start and end addresses to the beginning of their respective	\
	 cache lines to minimize the number of lines flushed.  */	\
      tmp = force_reg (Pmode, (TRAMP));					\
      emit_insn (gen_andsi3 (start_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      tmp = force_reg (Pmode,						\
		       plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));	\
      emit_insn (gen_andsi3 (end_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,	\
				  gen_reg_rtx (Pmode),			\
				  gen_reg_rtx (Pmode)));		\
    }									\
  else									\
    {									\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 56));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR));		\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 64));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT));			\
									\
      /* Create a fat pointer for the trampoline.  */			\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 16));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      force_reg (Pmode, plus_constant ((TRAMP), 32)));	\
      tmp = memory_address (Pmode, plus_constant ((TRAMP), 24));	\
      emit_move_insn (gen_rtx_MEM (Pmode, tmp),				\
		      gen_rtx_REG (Pmode, 27));				\
									\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  We align the	\
	 start and end addresses to the beginning of their respective	\
	 cache lines to minimize the number of lines flushed.  */	\
      tmp = force_reg (Pmode, plus_constant ((TRAMP), 32));		\
      emit_insn (gen_anddi3 (start_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      tmp = force_reg (Pmode,						\
		       plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));	\
      emit_insn (gen_anddi3 (end_addr, tmp,				\
			     GEN_INT (-MIN_CACHELINE_SIZE)));		\
      emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr, line_length));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, line_length,	\
				  gen_reg_rtx (Pmode),			\
				  gen_reg_rtx (Pmode)));		\
    }									\
}

/* Perform any machine-specific adjustment in the address of the trampoline.
   ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
   Adjust the trampoline address to point to the plabel at offset 44.  */
   
#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
  if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))

/* Implement `va_start' for varargs and stdarg.  */

#define EXPAND_BUILTIN_VA_START(valist, nextarg) \
  hppa_va_start (valist, nextarg)

/* Addressing modes, and classification of registers for them. 

   Using autoincrement addressing modes on PA8000 class machines is
   not profitable.  */

#define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)

#define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)

/* Macros to check register numbers against specific register classes.  */

/* The following macros assume that X is a hard or pseudo reg number.
   They give nonzero only if X is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

#define REGNO_OK_FOR_INDEX_P(X) \
  ((X) && ((X) < 32							\
   || (X >= FIRST_PSEUDO_REGISTER					\
       && reg_renumber							\
       && (unsigned) reg_renumber[X] < 32)))
#define REGNO_OK_FOR_BASE_P(X) \
  ((X) && ((X) < 32							\
   || (X >= FIRST_PSEUDO_REGISTER					\
       && reg_renumber							\
       && (unsigned) reg_renumber[X] < 32)))
#define REGNO_OK_FOR_FP_P(X) \
  (FP_REGNO_P (X)							\
   || (X >= FIRST_PSEUDO_REGISTER					\
       && reg_renumber							\
       && FP_REGNO_P (reg_renumber[X])))

/* Now macros that check whether X is a register and also,
   strictly, whether it is in a specified class.

   These macros are specific to the HP-PA, and may be used only
   in code for printing assembler insns and in conditions for
   define_optimization.  */

/* 1 if X is an fp register.  */

#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))

/* Maximum number of registers that can appear in a valid memory address.  */

#define MAX_REGS_PER_ADDRESS 2

/* Recognize any constant value that is a valid address except
   for symbolic addresses.  We get better CSE by rejecting them
   here and allowing hppa_legitimize_address to break them up.  We
   use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE.  */

#define CONSTANT_ADDRESS_P(X) \
  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
   || GET_CODE (X) == HIGH) 						\
   && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))

/* A C expression that is nonzero if we are using the new HP assembler.  */

#ifndef NEW_HP_ASSEMBLER
#define NEW_HP_ASSEMBLER 0
#endif

/* The macros below define the immediate range for CONST_INTS on
   the 64-bit port.  Constants in this range can be loaded in three
   instructions using a ldil/ldo/depdi sequence.  Constants outside
   this range are forced to the constant pool prior to reload.  */

#define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
#define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
#define LEGITIMATE_64BIT_CONST_INT_P(X) \
  ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)

/* A C expression that is nonzero if X is a legitimate constant for an
   immediate operand.

   We include all constant integers and constant doubles, but not
   floating-point, except for floating-point zero.  We reject LABEL_REFs
   if we're not using gas or the new HP assembler. 

   In 64-bit mode, we reject CONST_DOUBLES.  We also reject CONST_INTS
   that need more than three instructions to load prior to reload.  This
   limit is somewhat arbitrary.  It takes three instructions to load a
   CONST_INT from memory but two are memory accesses.  It may be better
   to increase the allowed range for CONST_INTS.  We may also be able
   to handle CONST_DOUBLES.  */

#define LEGITIMATE_CONSTANT_P(X)				\
  ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT			\
    || (X) == CONST0_RTX (GET_MODE (X)))			\
   && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF)	\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE)		\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_INT		\
	&& !(HOST_BITS_PER_WIDE_INT <= 32			\
	     || (reload_in_progress || reload_completed)	\
	     || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X))	\
	     || cint_ok_for_move (INTVAL (X))))			\
   && !function_label_operand (X, VOIDmode))

/* Target flags set on a symbol_ref.  */

/* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output.  */
#define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
#define SYMBOL_REF_REFERENCED_P(RTX) \
  ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)

/* Subroutines for EXTRA_CONSTRAINT.

   Return 1 iff OP is a pseudo which did not get a hard register and
   we are running the reload pass.  */
#define IS_RELOADING_PSEUDO_P(OP) \
  ((reload_in_progress					\
    && GET_CODE (OP) == REG				\
    && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
    && reg_renumber [REGNO (OP)] < 0))

/* Return 1 iff OP is a scaled or unscaled index address.  */
#define IS_INDEX_ADDR_P(OP) \
  (GET_CODE (OP) == PLUS				\
   && GET_MODE (OP) == Pmode				\
   && (GET_CODE (XEXP (OP, 0)) == MULT			\
       || GET_CODE (XEXP (OP, 1)) == MULT		\
       || (REG_P (XEXP (OP, 0))				\
	   && REG_P (XEXP (OP, 1)))))

/* Return 1 iff OP is a LO_SUM DLT address.  */
#define IS_LO_SUM_DLT_ADDR_P(OP) \
  (GET_CODE (OP) == LO_SUM				\
   && GET_MODE (OP) == Pmode				\
   && REG_P (XEXP (OP, 0))				\
   && REG_OK_FOR_BASE_P (XEXP (OP, 0))			\
   && GET_CODE (XEXP (OP, 1)) == UNSPEC)

/* Optional extra constraints for this machine. Borrowed from sparc.h.

   `A' is a LO_SUM DLT memory operand.

   `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
       memory operand.  Note that an unassigned pseudo register is such a
       memory operand.  Needed because reload will generate these things
       and then not re-recognize the insn, causing constrain_operands to
       fail.

   `R' is a scaled/unscaled indexed memory operand.

   `S' is the constant 31.

   `T' is for floating-point loads and stores.

   `U' is the constant 63.

   `W' is a register indirect memory operand.  We could allow short
       displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
       long displacement is valid.  This is only used for prefetch
       instructions with the `sl' completer.  */

#define EXTRA_CONSTRAINT(OP, C) \
  ((C) == 'Q' ?								\
   (IS_RELOADING_PSEUDO_P (OP)						\
    || (GET_CODE (OP) == MEM						\
	&& (reload_in_progress						\
	    || memory_address_p (GET_MODE (OP), XEXP (OP, 0)))		\
	&& !symbolic_memory_operand (OP, VOIDmode)			\
	&& !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))				\
	&& !IS_INDEX_ADDR_P (XEXP (OP, 0))))				\
   : ((C) == 'W' ?							\
      (GET_CODE (OP) == MEM						\
       && REG_P (XEXP (OP, 0))						\
       && REG_OK_FOR_BASE_P (XEXP (OP, 0)))				\
   : ((C) == 'A' ?							\
      (GET_CODE (OP) == MEM						\
       && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)))				\
   : ((C) == 'R' ?							\
      (GET_CODE (OP) == MEM						\
       && IS_INDEX_ADDR_P (XEXP (OP, 0)))				\
   : ((C) == 'T' ? 							\
      (GET_CODE (OP) == MEM						\
       && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))				\
       && !IS_INDEX_ADDR_P (XEXP (OP, 0))				\