bfin.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

  operands[2] = gen_rtx_EQ (BImode, op0, op1);
  /* If we have a BImode input, then we already have a compare result, and
     do not need to emit another comparison.  */
  if (GET_MODE (bfin_compare_op0) == BImode)
    {
      if (bfin_compare_op1 == const0_rtx)
	{
	  emit_insn (gen_cbranchbi4 (operands[2], op0, op1,
				     operands[0]));
	  DONE;
	}
      else
	abort ();
    }

  operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
})

(define_expand "bne"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		    (pc)))]
  ""
{
  rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
  /* If we have a BImode input, then we already have a compare result, and
     do not need to emit another comparison.  */
  if (GET_MODE (bfin_compare_op0) == BImode)
    {
      if (bfin_compare_op1 == const0_rtx)
	{
	  rtx cmp = gen_rtx_NE (BImode, op0, op1);
	  emit_insn (gen_cbranchbi4 (cmp, op0, op1, operands[0]));
	  DONE;
	}
      else
	abort ();
    }

  operands[1] = bfin_cc_rtx;	/* hard register: CC */
  operands[2] = gen_rtx_EQ (BImode, op0, op1);
  operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
})

(define_expand "bgt"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		    (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
})

(define_expand "bgtu"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		    (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
})

(define_expand "blt"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		    (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
})

(define_expand "bltu"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
})


(define_expand "bge"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LT (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
})

(define_expand "bgeu"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LTU (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_EQ (BImode, operands[1], const0_rtx);
})

(define_expand "ble"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LE (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
})

(define_expand "bleu"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		      (label_ref (match_operand 0 "" ""))
		      (pc)))
  ]
  ""
{
  operands[1] = bfin_cc_rtx;
  operands[2] = gen_rtx_LEU (BImode, bfin_compare_op0, bfin_compare_op1);
  operands[3] = gen_rtx_NE (BImode, operands[1], const0_rtx);
})

(define_insn "cbranchbi4"
  [(set (pc)
	(if_then_else
	 (match_operator 0 "bfin_cbranch_operator"
			 [(match_operand:BI 1 "cc_operand" "C")
			  (match_operand:BI 2 "immediate_operand" "P0")])
	 (label_ref (match_operand 3 "" ""))
	 (pc)))]
  ""
{
  asm_conditional_branch (insn, operands, 0, 0);
  return "";
}
  [(set_attr "type" "brcc")])

;; Special cbranch patterns to deal with the speculative load problem - see
;; bfin_reorg for details.

(define_insn "cbranch_predicted_taken"
  [(set (pc)
	(if_then_else
	 (match_operator 0 "bfin_cbranch_operator"
			 [(match_operand:BI 1 "cc_operand" "C")
			  (match_operand:BI 2 "immediate_operand" "P0")])
	 (label_ref (match_operand 3 "" ""))
	 (pc)))
   (unspec [(const_int 0)] UNSPEC_CBRANCH_TAKEN)]
  ""
{
  asm_conditional_branch (insn, operands, 0, 1);
  return "";
}
  [(set_attr "type" "brcc")])

(define_insn "cbranch_with_nops"
  [(set (pc)
	(if_then_else
	 (match_operator 0 "bfin_cbranch_operator"
			 [(match_operand:BI 1 "cc_operand" "C")
			  (match_operand:BI 2 "immediate_operand" "P0")])
	 (label_ref (match_operand 3 "" ""))
	 (pc)))
   (unspec [(match_operand 4 "immediate_operand" "")] UNSPEC_CBRANCH_NOPS)]
  "reload_completed"
{
  asm_conditional_branch (insn, operands, INTVAL (operands[4]), 0);
  return "";
}
  [(set_attr "type" "brcc")
   (set_attr "length" "6")])

;; setcc insns.  */
(define_expand "seq"
  [(set (match_dup 1) (eq:BI (match_dup 2) (match_dup 3)))
   (set (match_operand:SI 0 "validreg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
{
  operands[2] = bfin_compare_op0;
  operands[3] = bfin_compare_op1;
  operands[1] = bfin_cc_rtx;
})

(define_expand "slt"
  [(set (match_dup 1) (lt:BI (match_dup 2) (match_dup 3)))
   (set (match_operand:SI 0 "validreg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
{
   operands[2] = bfin_compare_op0;
   operands[3] = bfin_compare_op1;
   operands[1] = bfin_cc_rtx;
})

(define_expand "sle"
  [(set (match_dup 1) (le:BI (match_dup 2) (match_dup 3)))
   (set (match_operand:SI 0 "validreg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
{
   operands[2] = bfin_compare_op0;
   operands[3] = bfin_compare_op1;
   operands[1] = bfin_cc_rtx;
})

(define_expand "sltu"
  [(set (match_dup 1) (ltu:BI (match_dup 2) (match_dup 3)))
   (set (match_operand:SI 0 "validreg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
{
   operands[2] = bfin_compare_op0;
   operands[3] = bfin_compare_op1;
   operands[1] = bfin_cc_rtx;
})

(define_expand "sleu"
  [(set (match_dup 1) (leu:BI (match_dup 2) (match_dup 3)))
   (set (match_operand:SI 0 "validreg_operand" "")
	(ne:SI (match_dup 1) (const_int 0)))]
  ""
{
   operands[2] = bfin_compare_op0;
   operands[3] = bfin_compare_op1;
   operands[1] = bfin_cc_rtx;
})

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop;")

;;;;;;;;;;;;;;;;;;;;   CC2dreg   ;;;;;;;;;;;;;;;;;;;;;;;;;
(define_insn "movsibi"
  [(set (match_operand:BI 0 "cc_operand" "=C")
	(ne:BI (match_operand:SI 1 "validreg_operand" "d")
	       (const_int 0)))]
  ""
  "CC = %1;"
  [(set_attr "length" "2")])

(define_insn "movbisi"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(ne:SI (match_operand:BI 1 "cc_operand" "C")
	       (const_int 0)))]
  ""
  "%0 = CC;"
  [(set_attr "length" "2")])

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C")
	(eq:BI (match_operand:BI 1 "cc_operand" " 0")
	       (const_int 0)))]
  ""
  "%0 = ! %0;"    /*  NOT CC;"  */
  [(set_attr "type" "compare")])

;; Vector and DSP insns

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(ior:SI (ashift:SI (match_operand:SI 1 "validreg_operand" "d")
			   (const_int 24))
		(lshiftrt:SI (match_operand:SI 2 "validreg_operand" "d")
			     (const_int 8))))]
  ""
  "%0 = ALIGN8(%1, %2);"
  [(set_attr "type" "dsp32")])

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(ior:SI (ashift:SI (match_operand:SI 1 "validreg_operand" "d")
			   (const_int 16))
		(lshiftrt:SI (match_operand:SI 2 "validreg_operand" "d")
			     (const_int 16))))]
  ""
  "%0 = ALIGN16(%1, %2);"
  [(set_attr "type" "dsp32")])

(define_insn ""
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(ior:SI (ashift:SI (match_operand:SI 1 "validreg_operand" "d")
			   (const_int 8))
		(lshiftrt:SI (match_operand:SI 2 "validreg_operand" "d")
			     (const_int 24))))]
  ""
  "%0 = ALIGN24(%1, %2);"
  [(set_attr "type" "dsp32")])

;; Prologue and epilogue.

(define_expand "prologue"
  [(const_int 1)]
  ""
  "bfin_expand_prologue (); DONE;")

(define_expand "epilogue"
  [(const_int 1)]
  ""
  "bfin_expand_epilogue (1, 0); DONE;")

(define_expand "sibcall_epilogue"
  [(const_int 1)]
  ""
  "bfin_expand_epilogue (0, 0); DONE;")

(define_expand "eh_return"
  [(unspec_volatile [(match_operand:SI 0 "validreg_operand" "")]
		    UNSPEC_VOLATILE_EH_RETURN)]
  ""
{
  emit_move_insn (EH_RETURN_HANDLER_RTX, operands[0]);
  emit_insn (gen_eh_return_internal ());
  emit_barrier ();
})

(define_insn_and_split "eh_return_internal"
  [(unspec_volatile [(reg:SI REG_P2)] UNSPEC_VOLATILE_EH_RETURN)]
  ""
  "#"
  "reload_completed"
  [(const_int 1)]
  "bfin_expand_epilogue (1, 1); DONE;")

(define_insn "link"
  [(set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -4))) (reg:SI REG_RETS))
   (set (mem:SI (plus:SI (reg:SI REG_SP) (const_int -8))) (reg:SI REG_FP))
   (set (reg:SI REG_FP)
	(plus:SI (reg:SI REG_SP) (const_int -8)))
   (set (reg:SI REG_SP)
	(plus:SI (reg:SI REG_SP) (match_operand:SI 0 "immediate_operand" "i")))]
  ""
  "LINK %Z0;"
  [(set_attr "length" "4")])

(define_insn "unlink"
  [(set (reg:SI REG_FP) (mem:SI (reg:SI REG_FP)))
   (set (reg:SI REG_RETS) (mem:SI (plus:SI (reg:SI REG_FP) (const_int 4))))
   (set (reg:SI REG_SP) (plus:SI (reg:SI REG_FP) (const_int 8)))]
  ""
  "UNLINK;"
  [(set_attr "length" "4")])

;; This pattern is slightly clumsy.  The stack adjust must be the final SET in
;; the pattern, otherwise dwarf2out becomes very confused about which reg goes
;; where on the stack, since it goes through all elements of the parallel in
;; sequence.
(define_insn "push_multiple"
  [(match_parallel 0 "push_multiple_operation"
    [(unspec [(match_operand:SI 1 "immediate_operand" "i")] UNSPEC_PUSH_MULTIPLE)])]
  ""
{
  output_push_multiple (insn, operands);
  return "";
})

(define_insn "pop_multiple"
  [(match_parallel 0 "pop_multiple_operation"
    [(set (reg:SI REG_SP)
	  (plus:SI (reg:SI REG_SP) (match_operand:SI 1 "immediate_operand" "i")))])]
  ""
{
  output_pop_multiple (insn, operands);
  return "";
})

(define_insn "return_internal"
  [(return)
   (unspec [(match_operand 0 "immediate_operand" "i")] UNSPEC_RETURN)]
  "reload_completed"
{
  switch (INTVAL (operands[0]))
    {
    case EXCPT_HANDLER:
      return "rtx;";
    case NMI_HANDLER:
      return "rtn;";
    case INTERRUPT_HANDLER:
      return "rti;";
    case SUBROUTINE:
      return "rts;";
    }
  gcc_unreachable ();
})

;;; Vector instructions

(define_insn "addv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(plus:V2HI (match_operand:V2HI 1 "validreg_operand" "d")
		   (match_operand:V2HI 2 "validreg_operand" "d")))]
  ""
  "%0 = %1 +|+ %2;"
  [(set_attr "type" "dsp32")])

(define_insn "subv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(minus:V2HI (match_operand:V2HI 1 "validreg_operand" "d")
		   (match_operand:V2HI 2 "validreg_operand" "d")))]
  ""
  "%0 = %1 -|- %2;"
  [(set_attr "type" "dsp32")])

(define_insn "sminv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(smin:V2HI (match_operand:V2HI 1 "validreg_operand" "d")
		   (match_operand:V2HI 2 "validreg_operand" "d")))]
  ""
  "%0 = MIN (%1, %2) (V);"
  [(set_attr "type" "dsp32")])

(define_insn "smaxv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(smax:V2HI (match_operand:V2HI 1 "validreg_operand" "d")
		   (match_operand:V2HI 2 "validreg_operand" "d")))]
  ""
  "%0 = MAX (%1, %2) (V);"
  [(set_attr "type" "dsp32")])

(define_insn "mulv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(mult:V2HI (match_operand:V2HI 1 "validreg_operand" "d")
		   (match_operand:V2HI 2 "validreg_operand" "d")))]
  ""
  "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS);"
  [(set_attr "type" "dsp32")])

(define_insn "negv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(neg:V2HI (match_operand:V2HI 1 "validreg_operand" "d")))]
  ""
  "%0 = - %1 (V);"
  [(set_attr "type" "dsp32")])

(define_insn "absv2hi"
  [(set (match_operand:V2HI 0 "validreg_operand" "=d")
	(abs:V2HI (match_operand:V2HI 1 "validreg_operand" "d")))]
  ""
  "%0 = ABS %1 (V);"
  [(set_attr "type" "dsp32")])