bfin.md

Mac OS X 10.4.9 for x86 Source Code gcc 实现源代码

;; Bit test instructions

(define_insn "*not_bittst"
 [(set (match_operand:BI 0 "cc_operand" "=C")
       (eq:BI (zero_extract:SI (match_operand:SI 1 "validreg_operand" "d")
			       (const_int 1)
			       (match_operand:SI 2 "immediate_operand" "Ku5"))
	      (const_int 0)))]
 ""
 "cc = !BITTST (%1,%2);"
  [(set_attr "type" "alu0")])

(define_insn "*bittst"
 [(set (match_operand:BI 0 "cc_operand" "=C")
       (ne:BI (zero_extract:SI (match_operand:SI 1 "validreg_operand" "d")
			       (const_int 1)
			       (match_operand:SI 2 "immediate_operand" "Ku5"))
		(const_int 0)))]
 ""
 "cc = BITTST (%1,%2);"
  [(set_attr "type" "alu0")])

(define_insn_and_split "*bit_extract"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(zero_extract:SI (match_operand:SI 1 "validreg_operand" "d")
			 (const_int 1)
			 (match_operand:SI 2 "immediate_operand" "Ku5")))
   (clobber (reg:BI REG_CC))]
  ""
  "#"
  ""
  [(set (reg:BI REG_CC)
	(ne:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
	       (const_int 0)))
   (set (match_dup 0)
	(ne:SI (reg:BI REG_CC) (const_int 0)))])

(define_insn_and_split "*not_bit_extract"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(zero_extract:SI (not:SI (match_operand:SI 1 "validreg_operand" "d"))
			 (const_int 1)
			 (match_operand:SI 2 "immediate_operand" "Ku5")))
   (clobber (reg:BI REG_CC))]
  ""
  "#"
  ""
  [(set (reg:BI REG_CC)
	(eq:BI (zero_extract:SI (match_dup 1) (const_int 1) (match_dup 2))
	       (const_int 0)))
   (set (match_dup 0)
	(ne:SI (reg:BI REG_CC) (const_int 0)))])

(define_insn "*andsi_insn"
  [(set (match_operand:SI 0 "validreg_operand" "=d,d,d,d")
	(and:SI (match_operand:SI 1 "validreg_operand" "%0,d,d,d")
		(match_operand:SI 2 "rhs_andsi3_operand" "L,M1,M2,d")))]
  ""
  "@
   BITCLR (%0,%Y2);
   %0 = %T1 (Z);
   %0 = %h1 (Z);
   %0 = %1 & %2;"
  [(set_attr "type" "alu0")])

(define_expand "andsi3"
  [(set (match_operand:SI 0 "validreg_operand" "")
	(and:SI (match_operand:SI 1 "validreg_operand" "")
		(match_operand:SI 2 "general_operand" "")))]
  ""
{
  if (highbits_operand (operands[2], SImode))
    {
      operands[2] = GEN_INT (exact_log2 (-INTVAL (operands[2])));
      emit_insn (gen_ashrsi3 (operands[0], operands[1], operands[2]));
      emit_insn (gen_ashlsi3 (operands[0], operands[0], operands[2]));
      DONE;
    }
  if (! rhs_andsi3_operand (operands[2], SImode))
    operands[2] = force_reg (SImode, operands[2]);
})

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d,d")
	(ior:SI (match_operand:SI 1 "validreg_operand" "%0,d")
		(match_operand:SI 2 "regorlog2_operand" "J,d")))]
  ""
  "@
   BITSET (%0, %X2);
   %0 = %1 | %2;"
  [(set_attr "type" "alu0")])

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d,d")
	(xor:SI (match_operand:SI 1 "validreg_operand" "%0,d")
		  (match_operand:SI 2 "regorlog2_operand" "J,d")))]
  ""
  "@
   BITTGL (%0, %X2);
   %0 = %1 ^ %2;"
  [(set_attr "type" "alu0")])

(define_insn "smaxsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(smax:SI (match_operand:SI 1 "validreg_operand" "d")
		 (match_operand:SI 2 "validreg_operand" "d")))]
  ""
  "%0 =max(%1,%2);"
  [(set_attr "type" "dsp32")])

(define_insn "sminsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(smin:SI (match_operand:SI 1 "validreg_operand" "d")
		 (match_operand:SI 2 "validreg_operand" "d")))]
  ""
  "%0 =min(%1,%2);"
  [(set_attr "type" "dsp32")])

(define_insn "abssi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(abs:SI (match_operand:SI 1 "validreg_operand" " d")))]
  ""
  "%0 =abs %1;"
  [(set_attr "type" "dsp32")])


(define_insn "negsi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(neg:SI (match_operand:SI 1 "validreg_operand" " d")))]
  ""
  "%0 =-%1;"
  [(set_attr "type" "alu0")])

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(not:SI (match_operand:SI 1 "validreg_operand" " d")))]
  ""
  "%0 =~%1;"
  [(set_attr "type" "alu0")])

(define_insn "mulsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(mult:SI (match_operand:SI 1 "validreg_operand" "%0")
		 (match_operand:SI 2 "validreg_operand" "d")))]
  ""
  "%0 *=%2;"
  [(set_attr "type" "mult")])

(define_expand "ashlsi3"
  [(set (match_operand:SI 0 "validreg_operand" "")
        (ashift:SI (match_operand:SI 1 "validreg_operand" "")
                   (match_operand:SI 2 "nonmemory_operand" "")))]
  ""
{
 if (GET_CODE (operands[2]) == CONST_INT
     && ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
   {
     emit_insn (gen_movsi (operands[0], const0_rtx));
     DONE;
   }
})

(define_insn_and_split "*ashlsi3_insn"
  [(set (match_operand:SI 0 "validreg_operand" "=d,a,a,a")
	(ashift:SI (match_operand:SI 1 "validreg_operand" "0,a,a,a")
		   (match_operand:SI 2 "nonmemory_operand" "dKu5,P1,P2,?P3P4")))]
  ""
  "@
   %0 <<= %2;
   %0 = %1 + %1;
   %0 = %1 << %2;
   #"
  "PREG_P (operands[0]) && INTVAL (operands[2]) > 2"
  [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 2)))
   (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 3)))]
  "operands[3] = GEN_INT (INTVAL (operands[2]) - 2);"
  [(set_attr "type" "shft")])

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d")
	(ashiftrt:SI (match_operand:SI 1 "validreg_operand" "0")
		     (match_operand:SI 2 "nonmemory_operand" "dKu5")))]
  ""
  "%0 >>>= %2;"
  [(set_attr "type" "shft")])

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "validreg_operand" "=d,a")
	(lshiftrt:SI (match_operand:SI 1 "validreg_operand" " 0,a")
		     (match_operand:SI 2 "nonmemory_operand" "dKu5,P1P2")))]
  ""
  "@
   %0 >>= %2;
   %0 = %1 >> %2;"
  [(set_attr "type" "shft")])

;; A pattern to reload the equivalent of
;;   (set (Dreg) (plus (FP) (large_constant)))
;; or
;;   (set (dagreg) (plus (FP) (arbitrary_constant))) 
;; using a scratch register
(define_expand "reload_insi"
  [(parallel [(set (match_operand:SI 0 "validreg_operand" "=w")
                   (match_operand:SI 1 "fp_plus_const_operand" ""))
              (clobber (match_operand:SI 2 "validreg_operand" "=&a"))])]
  ""
{
  rtx fp_op = XEXP (operands[1], 0);
  rtx const_op = XEXP (operands[1], 1);
  rtx primary = operands[0];
  rtx scratch = operands[2];

  emit_move_insn (scratch, const_op);
  emit_insn (gen_addsi3 (scratch, scratch, fp_op));
  emit_move_insn (primary, scratch);
  DONE;
})

;; Jump instructions

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
{
  if (get_attr_length (insn) == 2)
    return "jump.s %0;";
  else
    return "jump.l %0;";
}
  [(set_attr "type" "br")])

(define_insn "indirect_jump"
  [(set (pc)
	(match_operand:SI 0 "validreg_operand" "a"))]
  ""
  "jump (%0);"
  [(set_attr "type" "misc")])

(define_expand "tablejump"
  [(parallel [(set (pc) (match_operand:SI 0 "validreg_operand" "a"))
              (use (label_ref (match_operand 1 "" "")))])]
  ""
{
  /* In PIC mode, the table entries are stored PC relative.
     Convert the relative address to an absolute address.  */
  if (flag_pic)
    {
      rtx op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);

      operands[0] = expand_simple_binop (Pmode, PLUS, operands[0],
					 op1, NULL_RTX, 0, OPTAB_DIRECT);
    }
})

(define_insn "*tablejump_internal"
  [(set (pc) (match_operand:SI 0 "validreg_operand" "a"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jump (%0);"
  [(set_attr "type" "misc")])

;;  Call instructions..

(define_expand "call"
  [(call (match_operand:SI 0 "" "")
	 (match_operand 1 "" ""))]
  ""
  "bfin_expand_call (NULL_RTX, operands[0], operands[1], 0); DONE;")

(define_expand "sibcall"
  [(parallel [(call (match_operand:SI 0 "" "")
		    (match_operand 1 "" ""))
	      (return)])]
  ""
  "bfin_expand_call (NULL_RTX, operands[0], operands[1], 1); DONE;")

(define_expand "call_value"
  [(set (match_operand 0 "validreg_operand" "")
         (call (match_operand:SI 1 "" "")
	       (match_operand 2 "" "")))]
  ""
  "bfin_expand_call (operands[0], operands[1], operands[2], 0); DONE;")

(define_expand "sibcall_value"
  [(parallel [(set (match_operand 0 "validreg_operand" "")
		   (call (match_operand:SI 1 "" "")
			 (match_operand 2 "" "")))
	      (return)])]
  ""
  "bfin_expand_call (operands[0], operands[1], operands[2], 1); DONE;")

(define_insn "*call_insn"
  [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "a,Q"))
	 (match_operand 1 "general_operand" "g,g"))]
  "! SIBLING_CALL_P (insn)
   && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)"
  "@
  call (%0);
  call %G0;"
  [(set_attr "type" "call")
   (set_attr "length" "2,4")])

(define_insn "*sibcall_insn"
  [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "z,Q"))
	 (match_operand 1 "general_operand" "g,g"))
   (return)]
  "SIBLING_CALL_P (insn)
   && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)"
  "@
  jump (%0);
  jump.l %G0;"
  [(set_attr "type" "br")
   (set_attr "length" "2,4")])

(define_insn "*call_value_insn"
  [(set (match_operand 0 "validreg_operand" "=d,d")
        (call (mem:SI (match_operand:SI 1 "call_insn_operand" "a,Q"))
	      (match_operand 2 "general_operand" "g,g")))]
  "! SIBLING_CALL_P (insn)
   && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)"
  "@
  call (%1);
  call %G1;"
  [(set_attr "type" "call")
   (set_attr "length" "2,4")])

(define_insn "*sibcall_value_insn"
  [(set (match_operand 0 "validreg_operand" "=d,d")
         (call (mem:SI (match_operand:SI 1 "call_insn_operand" "z,Q"))
	       (match_operand 2 "general_operand" "g,g")))
   (return)]
  "SIBLING_CALL_P (insn)
   && (GET_CODE (operands[0]) == SYMBOL_REF || GET_CODE (operands[0]) == REG)"
  "@
  jump (%1);
  jump.l %G1;"
  [(set_attr "type" "br")
   (set_attr "length" "2,4")])

;; Block move patterns

;; We cheat.  This copies one more word than operand 2 indicates.

(define_insn "rep_movsi"
  [(set (match_operand:SI 0 "validreg_operand" "=&a")
        (plus:SI (plus:SI (match_operand:SI 3 "validreg_operand" "0")
			  (ashift:SI (match_operand:SI 2 "validreg_operand" "a")
				     (const_int 2)))
		 (const_int 4)))
   (set (match_operand:SI 1 "validreg_operand" "=&b")
        (plus:SI (plus:SI (match_operand:SI 4 "validreg_operand" "1")
			  (ashift:SI (match_dup 2) (const_int 2)))
		 (const_int 4)))
   (set (mem:BLK (match_dup 3))
	(mem:BLK (match_dup 4)))
   (use (match_dup 2))
   (clobber (match_scratch:HI 5 "=&d"))]
  ""
  "lsetup (1f, 1f) LC1 = %2; %5 = [%4++]; 1: MNOP || [%3++] = %5 || %5 = [%4++]; [%3++] = %5;"
  [(set_attr "type" "misc")
   (set_attr "length" "16")])

(define_insn "rep_movhi"
  [(set (match_operand:SI 0 "validreg_operand" "=&a")
        (plus:SI (plus:SI (match_operand:SI 3 "validreg_operand" "0")
			  (ashift:SI (match_operand:SI 2 "validreg_operand" "a")
				     (const_int 1)))
		 (const_int 2)))
   (set (match_operand:SI 1 "validreg_operand" "=&b")
        (plus:SI (plus:SI (match_operand:SI 4 "validreg_operand" "1")
			  (ashift:SI (match_dup 2) (const_int 1)))
		 (const_int 2)))
   (set (mem:BLK (match_dup 3))
	(mem:BLK (match_dup 4)))
   (use (match_dup 2))
   (clobber (match_scratch:HI 5 "=&d"))]
  ""
  "lsetup (1f, 1f) LC1 = %2; %h5 = W[%4++]; 1: MNOP || W [%3++] = %5 || %h5 = W [%4++]; W [%3++] = %5;"
  [(set_attr "type" "misc")
   (set_attr "length" "16")])

(define_expand "movstrsi"
  [(match_operand:BLK 0 "general_operand" "")
   (match_operand:BLK 1 "general_operand" "")
   (match_operand:SI 2 "const_int_operand" "")
   (match_operand:SI 3 "const_int_operand" "")]
  ""
{
  if (bfin_expand_strmov (operands[0], operands[1], operands[2], operands[3]))
    DONE;
  FAIL;
})

;; Conditional branch patterns
;; The Blackfin has only few condition codes: eq, lt, lte, ltu, leu

;; The only outcome of this pattern is that global variables
;; bfin_compare_op[01] are set for use in bcond patterns.

(define_expand "cmpbi"
 [(set (cc0) (compare (match_operand:BI 0 "validreg_operand" "")
                      (match_operand:BI 1 "immediate_operand" "")))]
 ""
{
  bfin_compare_op0 = operands[0];
  bfin_compare_op1 = operands[1];
  DONE;
})

(define_expand "cmpsi"
 [(set (cc0) (compare (match_operand:SI 0 "validreg_operand" "")
                      (match_operand:SI 1 "nonmemory_operand" "")))]
 ""
{
  bfin_compare_op0 = operands[0];
  bfin_compare_op1 = operands[1];
  DONE;
})

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C,C")
        (eq:BI (match_operand:SI 1 "validreg_operand" "d,a")
               (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
  ""
  "cc =%1==%2;"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C,C")
        (ne:BI (match_operand:SI 1 "validreg_operand" "d,a")
               (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
  "0"
  "cc =%1!=%2;"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C,C")
        (lt:BI (match_operand:SI 1 "validreg_operand" "d,a")
               (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
  ""
  "cc =%1<%2;"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C,C")
        (le:BI (match_operand:SI 1 "validreg_operand" "d,a")
               (match_operand:SI 2 "nonmemory_operand" "dKs3,aKs3")))]
  ""
  "cc =%1<=%2;"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C,C")
        (leu:BI (match_operand:SI 1 "validreg_operand" "d,a")
                (match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))]
  ""
  "cc =%1<=%2 (iu);"
  [(set_attr "type" "compare")])

(define_insn ""
  [(set (match_operand:BI 0 "cc_operand" "=C,C")
        (ltu:BI (match_operand:SI 1 "validreg_operand" "d,a")
                (match_operand:SI 2 "nonmemory_operand" "dKu3,aKu3")))]
  ""
  "cc =%1<%2 (iu);"
  [(set_attr "type" "compare")])

(define_expand "beq"
  [(set (match_dup 1) (match_dup 2))
   (set (pc)
	(if_then_else (match_dup 3)
		   (label_ref (match_operand 0 "" ""))
		   (pc)))]
  ""
{
  rtx op0 = bfin_compare_op0, op1 = bfin_compare_op1;
  operands[1] = bfin_cc_rtx;	/* hard register: CC */